IDEC DD3S Series - Terminal Connection

6
DD3S Series Display Units
Terminal Connection
Connection Diagram Terminal Arrangement Internal Input Circuit
Binary Display Unit
Standard Standard
Decimal/Hexadecimal/Extra Decimal Display Units
Standard Standard
Positive Logic
2-color Alternate Display 2-color Alternate Display
Negative Logic
Zero-suppress Zero-suppress
Character Display Unit
Positive Logic
Negative Logic
(Terminal No.)
Power
+
–
1
Vcc
GND
Latch
BL
LT
DP
4
12
8
10
9
5
7
6
2
Regulating Circuit
Input Circuit
Decoder
1. NC
12. GND
11. NC
10.
+
+
9.
8. Latch
7. BL
6. LT
5. 1
4. Vcc
3. NC
2. DP
−
–
Power
12 to 24V DC
(Terminal No.)
Vcc
GND
Latch
A
(
2
)
B
(
2
)
C
(
2
)
D
(
2
)
BL
LT
DP
4
12
8
10
3
5
9
7
6
2
1
2
3
0
(Terminal No.)
Power
Regulating Circuit
Input Circuit
Decoder
1. NC
12. GND
11. NC
10. A
(
2
)
9. D
(
2
)
8. Latch
7. BL
6. LT
5. C
(
2
)
4. Vcc
3. B
(
2
)
2. DP
0
3
2
1
(Terminal No.)
+
−
Power
12 to 24V DC
200 kΩ
200 kΩ
12 kΩ
Data Input
GND
Vcc
GND
Latch
BL
R/G
DP
4
12
8
10
3
5
9
7
6
2
(Terminal No.)
Power
Regulating Circuit
Input Circuit
Decoder
A
(
2
)
B
(
2
)
C
(
2
)
D
(
2
)
1
2
3
0
1.
12.
11.
10.
9.
8.
7.
6. R/G
5.
4.
3.
2.
NC
GND
NC
A
(
2
)
D
(
2
)
Latch
BL
C
(
2
)
Vcc
B
(
2
)
DP
0
3
2
1
(Terminal No.)
+
−
Power
12 to 24V DC
200 kΩ
200 kΩ
12 kΩ
Data Inpu
t
GND
12 to 24V DC
Vcc
GND
Latch
BL
LT
RBI
RBO
DP
4
12
8
10
3
5
9
7
6
1
11
2
(Terminal No.)
Power
Regulating Circuit
Input Circuit
Decoder
A
(
2
)
B
(
2
)
C
(
2
)
D
(
2
)
1
2
3
0
1. RBI
12.
11. RBO
10.
9.
8.
7.
6.
5.
4.
3.
2.
GND
A
(
2
)
D
(
2
)
Latch
BL
LT
C
(
2
)
Vcc
B
(
2
)
DP
0
3
2
1
(Terminal No.)
+
−
Power
12 to 24V DC
Power
Control Input
Regulating Circuit
Input Circuit
Microprocessor
Data Input
Driver
5 x 7 dot matrix LED
(Terminal No.)
Latch
Power
Data Input
(Terminal No.)
Control Input
Latch
470 kΩ
470 kΩ
12 kΩ
Data Inpu
t
GND
470 kΩ
470 kΩ
12 kΩ
Data Inpu
t
GND
12 to 24V DC