User Guide 9 of 25 002-32910 Rev. *A
2021-09-29
Getting started with TRAVEO™ T2G entry family starter kit
Download and debug with starter kit
3 Download and debug with starter kit
There are two debugging methods with IAR EWARM:
• Debugging with code downloaded on to RAM
• Debugging with code downloaded on to the flash memory (described in this document)
SDL supports three types of workspaces under flash memory debugging as listed in Table 3.
Table 3 IAR Flash workspaces and functions
Number of
cores supported
Single core CM0+ workspace
“tviibe1m_flash_cm0plus_template”
Single core download and
debug for CM0+ core.
Single core CM4 workspace
“tviibe1m_flash_cm4_mc_template”
Single core download and
debug for CM4 core; works as
client/slave workspace in
multicore configuration.
Note: It is possible to
debug only with
CM4, when CM0+
executes some
code, thus
enabling CM4.
Dual core CM0+ and CM4 workspace
“tviibe1m_flash_cm0plus_cm4_template”
Dual core download and debug
for CM0+ and CM4 cores; works
as master workspace in
multicore configuration.
Note: Both CM0+ and CM4 can do normal code execution, but from an architectural point only CM4 is
considered as the application core. After a reset, the default core is always the CM0+ core. To
enable the CM4 core, CM0+ must call Cy_SysEnableApplCore (). In the SDL, this is usually done
within main_cm0plus.c.
Before downloading and debugging with the multicore master project, you must build the multicore slave
project for the application core (which is CM4 here).
Open the master workspace (dual core CM0+ and CM4 workspaces) for multicore debugging. The slave
workspace (single core CM4 workspace) will automatically open from the master workspace when you click
Download and Debug.
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