Integra DTR-6.5 - Page 58

DTR-6.5
IC BLOCK DIAGRAMS AND DESCRIPTIONS
M66005-0001AFP(FL tube drive IC)
~
CS
SCK
SDATA
RESET
Xin
Xout
Vcc1
Vcc2
SERIAL
RECEIVE
CIRCUIT
DISPLAY
CODE RAM
(8 bits
16)
CODE/ COMMAND CONTROL CIRCUIT
INDICATOR
CONTROL
REGISTER
CLOCK
GENERATOR
CIRCUIT
DISPLAY
CONTROLLER
RAM
write
code
selector
CGROM
(35 bits 160)
CGRAM
(35 bits 16)
SEGMENT OUTPUT CIRCUIT
DIGIT
OUTPUT
CIRCUIT
SEG36
SEG28
SEG27
SEG01
P1
P0
Vss
Vp
DECODER
DECODER
~~
DIG16/SEG40
DIG13/SEG37
~
~
DIG12
DIG01
~
1
12
61
64
22
20
21
13
16
15
14
19
60
59
33
32
~
~
31
23
18
17
SEGMENT/DIGIT SELECT/OUTPUT CIRCUIT
w w w . x i a o y u 1 6 3 . c o m
Q Q
3
7
6 3
1 5 1 5
0 9 9
2
8 9
4 2
9 8
T E L 1 3 9 4 2 2 9 6 5 1 3 9 9 2 8 9 4 2 9 8 0 5 1 5 1 3 6 7 3
Q Q
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