1 Overview of the 34934A
34 Keysight 34934A User’s Guide
8x32 Matrices
8x32 Topology
You can select the 8x32 matrix configuration by setting jumpers on the
appropriate terminal block or configuration block, or by D-Sub wiring.
Once configured for 8x32, the 34934A creates two matrices, each with 256
crosspoint non-latching reed relays organized in an 8-row by 32-column
configuration. You can operate these as two independent 1-wire matrices (MH,
ML) or as a single 2-wire matrix.
In 1-wire operation, the two matrices are:
– MH: uses H (high) columns C1H-C32H and H rows R1H-R8H.
– ML: uses L (low) columns C1L-C32L and L rows R1L-R8L.
In 2-wire operation, a single matrix is formed by “pairing” MH and ML. The matrix
uses both the H and L columns and rows; C1H-32H, C1L-C32L, R1H-R8H and
R1L-R8L.
As the examples illustrate, no physical matrix configuration changes are required
for 2-wire operation. You wire your test devices between corresponding high and
low matrix terminals or D-Sub pins, then operate the matrix in 2-wire mode by
using SCPI paired commands (e.g. ROUT:OPEN:PAIR).
In either mode of operation, each matrix (MH, ML) is created by jumpering the
columns
on two of the 4x32 relay banks together. This is done automatically
through the “CONFIG” jumpers on the terminal and configuration blocks, or by
shorting pins between your D-Sub cables. The column jumpers are not indicated
in the examples.
On the 34934T-002 terminal block, there are redundant “H” and “L” sets of
terminals provided for columns 1-32, one set on each side of the block. The
column terminals on each side of the block are shorted (by traces within the
block) to their like-labeled counterparts on the other; you may make any column
connection to the appropriate terminal on either side.
8x32 1-Wire Operation, Test Circuit Examples
The two examples below each show two 1-wire circuit paths through the matrix.
The upper example (MH) shows one path with the DUT and test instrument both
connected to the columns; the other path shows the test instrument connected
through a row protection resistor. The lower example (ML) shows both paths
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