LG DP372D - Sdram Clock; Tray Open;Close Signal

3-13
Copyright © 2008 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
DCKE
BA1
SDCKE
DBA1
DBA0 BA0
DCLKSDCLK
R207
33R207 33
R206 33R206 33
R205
33R205 33
R208
151R208 151
2. SDRAM CLOCK
3. TRAY OPEN/CLOSE SIGNAL
FIG 2-1
7
TROPEN
S3.3V
Tray_Open_SW
C322
104
C322
104
SW301
SW PUSHBUTTON
SW301
SW PUSHBUTTON
14
23
C321
104
C321
104
R332
10K
R332
10K
FIG 3-1
8
8
7
DCLK=128MHz, Vp-p=1.77, Vmax=2.35V
OPEN
CLOSE