48 Chapter 4: Matrox Rapixo CXP hardware reference
You would typically use standard Matrox FPGA configurations. You can also chose
to implement processing on your own, using the Matrox FPGA Developers
Toolkit (FDK) and C++. If required, Matrox’s FPGA design services can be
employed to develop an application-specific FPGA configuration.
Once the Processing FPGA is programmed, you can then make use of its
functionality using MIL. Refer to Using MIL with a Processing FPGA chapter in
the MIL User Guide for more information.
Host interface
The Matrox Rapixo CXP PCIe Host interface is capable of high-speed DMA
transfers to Host memory, or other memory mapped onto the PCIe bus. The
DMA write engine of the Host interface is capable of performing the transfers
without the help of the Host CPU.
Quad CXP-6 uses PCIe 2.1 and both Quad CXP-12 and Pro Quad CXP-12 use
PCIe 3.1 technology to communicate with the Host. Under optimum conditions,
Matrox Rapixo CXP can send data to the Host at a peak transfer rate of up to
8 Gbytes/sec. Optimum conditions include using the board in a PCIe 3.x slot
with 8 active lanes, and using a 256-byte or 512-byte payload.
DMA write performance is chipset and computer dependent, and is slightly
affected by the image size and alignment in Host memory.
The Matrox Rapixo CXP Host interface has four DMA write contexts, which act
independently, simulating four DMA write engines running in parallel. The
presence of multiple DMA contexts does not change the maximum bandwidth,
but can help reduce latency.
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