_)
Theory of Operation
2-5
2.2.6 Microprocessor Clock Synthesizer
The clock source for the
1-1P
system
is
generated by the ASFIC CMP (U0221
).
Upon power-up the
synthesizer
IC (FRAC-N) generates a 16.8 MHz waveform that
is
routed from the RF section to the
ASFIC
CMP,
pin 34. For the main board controller the ASFIC CMP uses 16.8
MHz
as a reference
input
clock signal for its internal synthesizer. The ASFIC
CMP,
in
addition
to
the audio circuit, has a
programmable synthesizer which can generate a synthesized signal ranging from 1200Hz
to
32.769MHz
in
1200Hz steps.
When power is first
applied, the ASFIC CMP generates its default 3.6864MHz CMOS square wave
UP CLK (on U0221, pin 28) and this
is
routed
to
the
1-1P
(U0101, pin 90). After the
1-1P
starts
operation, it reprograms the
ASFIC CMP clock synthesizer to a higher UP CLK frequency (usually
7.3728 or 14.7456 MHz) and continues operation.
The
ASFIC CMP may be reprogrammed to change the clock synthesizer frequencies at various
times depending on the software features that are executing.
In
addition, the clock frequency of the
synthesizer
is
changed in small amounts if there is a possibility
of
harmonics
of
this clock source
interfering with the desired radio receive frequency.
The
ASFIC CMP synthesizer loop uses C0245, C0246 and R0241
to
set the switching time and jitter
of
the
clock output.
If
the synthesizer cannot generate the required clock frequency it switches back
to its
default 3.6864MHz output.
Because the
ASFIC CMP synthesizer and the
1-1P
do
not operate without the 16.8 MHz reference
clock, the synthesizer and the voltage regulators should be checked first in debugging the system.
The
1-1P
uses crystal oscillator Y0131 and associated components
to
form a real time clock used
to
display the time on control heads (with display) or as time stamp for incoming calls or messages.
The
real time clock
is
powered from the voltage VSTBY to keep running while the radio
is
switched
off.
If
the
radio is disconnected from the supply voltage, the time must be reset.
2.2.7 Serial Peripheral Interface (SPI)
The
1-1P
communicates to many of the IC's through its SPI port. This port consists
of
SPI TRANSMIT
DATA
(MOSI) (U0101, pin 100), SPI RECEIVE
DATA
(MISO) (U01 01, pin 99), SPI CLK (U0101, pin
1)
and chip select lines going
to
the various ICs. The BUS is a synchronous bus, in that the timing
clock signal CLK
is
sent while SPI data (SPI TRANSMIT or RECEIVE) is sent. Therefore, whenever
there
is
activity on either SPI TRANSMIT
DATA
or SPI RECEIVE
DATA
there should be a uniform
signal on CLK.
The
SPI TRANSMIT
DATA
sends serial data from the
1-1P
to a device, and SPI RECEIVE
DATA
is
sends data from a device to the
IJP.
On
the controller there are two ICs on
the
SPI BUS: ASFIC CMP
(U0221, pin 22), and EEPROM (U0111, pin 5).
In
the
RF
section there are two ICs on the SPI BUS:
FRAC-N Synthesizer, and the
Power Control
IC
(PCIC). The SPI TRANSMIT
DATA
and CLK lines
going to the
RF
section are filtered by L0481/R0481 and L0482/R0482 to minimize noise. The chip
select line CSX from U0101, pin 2 is shared
by
the ASFIC
CMP,
FRAC-N Synthesizer, and PCIC.
Each
of
these IC's check the SPI data and when the sent address information matches the IC's
address, the data that follows is processed. The chip select lines for the EEPROM (EE CS), voice
storage (VS CS), expansion board
(EXP1 CS, EXP2 CS) and option board (OPT CS) are decoded
by the address decoder
UO
141.
When the
1-1P
needs
to
program any
of
these IC's it brings the chip select line CSX
to
a logic 0 and
then sends the proper data and
clock signals. The amount
of
data sent varies, for example the
ASFIC CMP can receive up to
19
bytes (152 bits) while the PCIC can receive up to 6 bytes (48 bits).
After the data is sent, the chip
select line is returned to logic
1.
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