2-28
Theory
of
Operation
programmed at several points across the frequency range
of
the transmitter to offset frequency
response variations
of
the transmitter's power detector circuits.
The
PCIC provides a
de
output voltage at pin 4
(I
NT) which sets the drain current
of
the first stage
(U3401) via current control opamp U3503-1. This adjusts the transmitter power output to the
intended value. Variations
in
forward transmitter power cause the de voltage at pin 1 to change, and
the PCIC adjusts the control voltage above or below its nominal value to raise or lower output power.
Capacitors C3501-3, in conjunction with resistors and integrators within the PCIC, control the
transmitter power-rise (key-up) and power-decay (de-key) characteristic to minimize splatter into
adjacent channels.
U3502
is
a temperature-sensing device, which monitors the circuit board temperature
in
the vicinity
of
the transmitter driver and final devices, and provides a de voltage to the PCIC (TEMP, pin 29)
proportional to temperature. If the de voltage produced exceeds the set threshold
in
the PCIC, the
transmitter output power is reduced so as to reduce the transmitter temperature.
The power control circuitry includes a safety switch (S3501) that consists
of
a conductive portion
of
the rubber pad which pushes the RF final transistor
03440
against the chassis. When the chassis
cover and rubber pad are
properly assembled, the conductive portion
of
the pad contacts a pattern
on the circuit board, electrically closing switch S3501. If the cover and pad are not
in
place, switch
S3501
is
open-circuited and the power control circuit
is
disabled. This prevents thermal damage of
the RF final transistor which might occur if the transmitter
is
operated without adequate heatsinking.
2.9 Frequency Synthesis
The synthesizer subsystem consists
of
the reference oscillator, the low voltage fraction a
I-N
synthesizer (LVFRAC-N), and the Voltage Controlled Oscillator VCO.
2.9.1
Reference Oscillator
The reference oscillator (Y3201) contains a temperature compensated crystal oscillator with a
frequency
of
16.8 MHz. An Analog-to-Digital (AID) converter internal to U3201 (LVFRAC-N) and
controlled by the
IJP
via serial interface (SRL) sets the voltage at the warp output
of
U3201, pin 25 to
set the frequency
of
the oscillator. The output of the oscillator (pin 3
of
Y3201) is applied to pin
23
(XTAL
1)
of
U3201 via an
RC
series combination.
2.9.2 Fractionai-N Synthesizer
The LVFRAC-N synthesizer
IC
(U3201) consists
of
a pre-scaler, a programmable loop divider,
control divider logic, a phase detector, a charge pump, an A/D converter for low frequency digital
modulation,
a balanced attenuator to balance the high frequency analog modulation and low
frequency digital modulation, a 13V positive voltage multiplier, a serial interface for control, and
finally a super filter for the regulated 5 volts.
A voltage
of
5V applied to the super filter input (U3201 pin 30) supplies an output voltage
of
4.5 Vdc
(VSF) at pin 28.
It
supplies the VCO and the synthesizer charge pump resistor network. The
synthesizer supply voltage is provided by the 5V regulator U3202.
In
order to generate a high voltage to supply the phase detector (charge pump) output stage at pin
VCP (U3201 pin 47), a voltage of 13 Vdc
is
being generated by the positive voltage multiplier
circuitry (D3201 and C3212-13). This voltage multiplier
is
basically a diode capacitor network driven
by two signals (1.05MHz) 180 degrees out
of
phase (U3201-14 and -15).
_)
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