EasyManua.ls Logo

Motorola CDM1550-LS+ - Fractionai-N Synthesizer

Motorola CDM1550-LS+
114 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Loading...
2-22 Theory of Operation
2.6.2 Fractionai-N Synthesizer
The LVFRAC-N synthesizer
IC
(U3201) consists
of
a pre-scaler, a programmable loop divider,
control divider logic, a phase detector, a charge pump,
an
AID
converter for low frequency digital
modulation,
a balance attenuator to balance the high frequency analog modulation and low
frequency digital modulation, a
13
volt positive voltage multiplier, a serial interface for control, and
finally a super filter for the regulated 5 volts.
DATA (U0101
PIN
100)
CLOCK (U0101
PIN
1)
CSX (U0101
PIN
2)
MOD IN (U0221 PIN 40)
7
DATA
8
CLK
9 CEX
----~
10
13,
30
MOD
IN
VCC,DC5V
VDD, DC5V
XTAL1
U3201
LOW VOLTAGE
FRACTIONAL-N
SYNTHESIZER
WARP
LOCK
1-4~~
-
LOCK (U0101
PIN
56)
FREFOUT
1-
1
:....:.
9~
--
FREF (U0221
PIN
34)
GND
6, 22,
33,
44
lOUT
1-4
=
3~
-
-!
!ADAPT
1-4
.:.:::5
_..
_
-!
MODOUT
1-
4
-'-'
1
~
------,
AU
X4
1--'3,_____.__...
AUX2
1-1
~__...
AUX3
1--'
2=---il~
---l
TX
RF
INJEC
TI
ON
(1ST STAGE OF
PA)
PRESCALER
IN
Figure 2-9. 200 MHz Synthesizer Block Diagram
A
voltage
of
5V applied to the super filter input (U3201 pin 30) supplies an output voltage
of
4.5 Vdc
(VSF) at pin 28. It supplies the VCO, VCO modulation bias circuit (via R3363) and the synthesizer
charge pump resistor network (R3251, R3252). The synthesizer supply voltage
is
provided
by
the
5V regulator U3211.
In
order to generate a high voltage to supply the phase detector (charge pump) output stage at pin
VCP (U3201-47), a voltage of
13
Vdc is being generated by the positive voltage multiplier circuits
(D3201, C3202, C3203). This voltage multiplier is basically a diode capacitor network driven by two
signals (1.05MHz) 180 degrees out
of
phase signals (U3201-14 and -15).
Output LOCK (U3201-4) provides information about the lock status
of
the synthesizer loop. A high
level at this output indicates a stable loop.
IC
U3201 provides the 16.8 MHz reference frequency at
pin 19.
The
serial interface (SRL) is connected to the
IJP
via the data line
DATA
(U3201-7), clock line CLK
(U3201-8), and chip enable line CSX (U3201-9).

Table of Contents

Other manuals for Motorola CDM1550-LS+

Related product manuals