_)
Theory
of
Operation
2-19
The IF output from T3301
is
applied to a diplexer (L3025, C3061, R3032, L3181) which matches the
44.85 MHz IF signal to the crystal filter and terminates the mixer into
500
at all other frequencies.
2.4.2 Receiver Back
End
The receiver back end
is
a dual conversion design. High IF selectivity is provided by FL3101, a 4-
pole fundamental mode 44.85 MHz crystal filter with a minimum 3
dB
bandwidth
of
7.5 kHz. The
output is fed to
IF
amplifier stage 03110, whose input impedance is adjusted using feedback to
provide a proper terminating impedance for the filter. The output
of
03110
is
applied to the input
of
the receiver IFIC U3101. Diode CR3200 prevents overdriving the IFIC.
The IFIC is a low-voltage monolithic FM IF system incorporating a mixer/oscillator, two limiting IF
amplifiers, quadrature detector, logarithmic received signal strength indicator (RSSI), voltage
regulator and audio and RSSI op amps. The second LO frequency
is
determined by Y3100.
Additional
IF
selectivity
is
provided
by
two ceramic filters,
Y31
04
(between the second mixer and
IF
amp) and FL3106 (between the
IF
amp and the limiter input). Y3104
is
a 4 element filter with a BW6
=12kHz.
FL3106
is
a 6 element filter with a BW6
=9kHz.
These bandwidths are optimum for 12.5
kHz channel spacing systems. Ceramic resonator
Y31
02 provides phase
vs.
frequency
characteristic required by the quadrature detector, with
90
degree phase shift occurring at
455kHz.
Buffer 03111 provides a lower driving impedance from the limiter to the resonator, improving the
IF
waveform and lowering distortion.
2.5 Transmitter Power Amplifier
(PA)
25
W
The radio's 25 W
PAis
a three-stage amplifier used to amplify the output from the VCOBIC to the
radio transmit level. The line-up consists
of
three stages which utilize LDMOS technology. The gain
of
the first stage (U3401)
is
adjustable, controlled by pin 4
of
PCIC (U3501) via U3402-1 (VCNTRL).
It is followed
by
an
LDMOS pre-driver stage
(03421)
and an LDMOS final stage (03441).
Vcontrol
To
Microprocessor
Bias 1
PA
PWR
SET
PCIC
To
Microprocessor
Figure 2-8. 200 MHz Transmitter Block Diagram
Antenna
Devices U3401 and 03421 are surface mounted. 03441 is directly attached to the heat sink.
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