Motorola R-2001A - Page 150

P1
4
1 0.24 5 MHz
I
l
SYNTH 10 MHz
,7 ) I
SYNTH 10 0Hz
11 -86 ) I
ADRS BUS AD-A 15
91-98 ) I DAT A B US DO -D
7
58) I NMI
i9) I RESET
7 0~
87~MA
88~
90 ~ R/W
I
I
I
I
I
I
U25 --~~
I
I
- I
T P3
I
ZE RO
BE AT
DET
U32
10.245 MHz VCO TV
~
AF BUS EN2
P1
..L( 9
I
RF ADRS BUS 0-3 37-44
RFQATABUS0- 3 50,55 - 57
AF ADRS BUS 0-3 1 3, 15 , 1 7. 19
AF D ATA BUS 0-3 29-36
I
I
I
I
I
I
I
I
I
BEAT !NO I ( 21
Figure 13-1. Processor 1/0 A7
Block Diagram
13-3,13-4
8521-32