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Chapter 4 Analog Input
Using an External Source
Use one of the following external signals as the source of AI Convert Clock:
• PFI <0..15>
•RTSI <0..7>
• PXI_STAR
• Analog Comparison Event (an analog trigger)
Routing AI Convert Clock Signal to an Output Terminal
You can route AI Convert Clock (as an active low signal) out to any PFI <0..15>, RTSI <0..7>,
or PXIe_DSTARC terminal.
All PFI terminals are configured as inputs by default.
Using a Delay from Sample Clock to Convert Clock
When using the AI timing engine to generate your Convert Clock, you can also specify a
configurable delay from AI Sample Clock to the first AI Convert Clock pulse within the sample.
By default, this delay is three ticks of AI Convert Clock Timebase.
Figure 4-17 shows the relationship of AI Sample Clock to AI Convert Clock.
Figure 4-17. AI Sample Clock and AI Convert Clock
Other Timing Requirements
The sample and conversion level timing of MIO X Series devices work such that some clock
signals are gated off unless the proper timing requirements are met. For example, the device
ignores both AI Sample Clock and AI Convert Clock until it receives a valid AI Start Trigger
signal. Similarly, the device ignores all AI Convert Clock pulses until it recognizes an AI Sample
Clock pulse. Once the device receives the correct number of AI Convert Clock pulses, it ignores
subsequent AI Convert Clock pulses until it receives another AI Sample Clock. However, after
AI Convert Clock Timebase
AI Sample Clock
AI Convert Clock
Delay from
Sample
Clock
Convert
Period
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