Figure 13. sbRIO-9637 Pedestal Dimensions
A
B
C
D
E
F
46.10 (1.815)
54.22 (2.135)
58.27 (2.294)
67.40 (2.654)
72.75 (2.864)
81.89 (3.224)
4.10 (0.162)
60.83 (2.395)
47.76 (1.880)
28.69 (1.130)
18.25 (0.718)
67.88 (2.672)
41.79 (1.645)
46.93 (1.847)
48.30 (1.901)
55.35 (2.179)
57.19 (2.252)
76.26 (3.002)
34.39 (1.354)
29.25 (1.152)
15.84 (0.624)
14.82 (0.583)
6.69 (0.263)
4.71 (0.185)
0.0 (0.000)
0.0 (0.000)
The following table provides the pedestal height from board surface for each corresponding
component shown in the previous figure.
Table 1. Pedestal Height from Board Surface
Designation Pedestal Corresponding
Component
Pedestal Height from Board Surface
A ENET PHY 2.05 mm (0.081 in.)
B USB PHY 2.00 mm (0.079 in.)
C CPLD 2.20 mm (0.087 in.)
D NAND Flash 2.16 mm (0.085 in.)
E DDR Memory 2.32 mm (0.091 in.)
F CPU/FPGA 2.51 mm (0.099 in.)
Note Pedestals of the same dimensions are allowed to violate the primary side
maximum component height keepaway restrictions.
Note Gap-filling thermal interface materials between the components and
pedestals confined to within the indicated region are allowed to violate the primary
side maximum component height keepaway restrictions.
NI sbRIO-9637 User Manual | © National Instruments | 15
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com
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