PRELIMINARY INFORMATION
Jetson AGX Orin Series Tuning and Compliance Guide DA-11040-001_v0.7 | 10
PCIe Compliance Testing Reference
Jetson AGX Orin series modules (referred to as Orin module) include several high-speed UPHY
interfaces supporting protocols such as USB-3, PCIe, and UFS. Interface lanes can flexibly be
mapped to PADs to form a mix of different protocols.
The Orin module supports several PCIe controllers. The controllers can be assigned to
multiple UPHY lanes in three different domains (UPHY0, UPHY1, and UPHY2), in a mix with
other controllers such as USB and MGBE in x1, x2, x4, and x8 configurations. Refer to the
Jetson AGX Orin Series Data Sheet
, the
Jetson AGX Orin Design Guide,
and the
Orin Technical
Reference Manual
(TRM) for details.
The base requirement for all designs is to adhere to the
Jetson AGX Orin Design Guide
layout
guidelines. PCIe shall pass all physical layer (PHY) specifications and conformance with no
change in production (PROD) register settings. Changing the PROD settings is not
recommended.
!
CAUTION: Compliance testing and characterization as described in this application note covers
PCIe Gen1 to Gen3 only.
The Tx test procedures described in this application note are not recommended for Gen4 and
up, since they introduce higher amount of noise for measurements greater than Gen3
specifications. For higher speeds, functional testing and in-circuit test methods may be used.
Such as Eye Opening Monitor (EOM)–an NVIDIA built-in UPHY facility, or PCIe “Lane
Margining”–a mandatory support for devices with 16 GT/s or higher.
References
The following are PCIe specifications and NVIDIA documents references for PCIe compliance
testing.
PCISIG specifications:
• PCI Express Architecture PHY Test Specification 3.0 (Gen1, Gen2, and Gen3)
• PCI Express Architecture PHY Test Specification 4.0 (Gen1, Gen2, Gen3, and Gen4)
NVIDIA documents:
• Jetson AGX Orin Design Guide
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