Power Supply
MPC5746R Hardware Design Guide, Rev. 1
NXP Semiconductors 19
3. After both LV, HV and temperature POWERUP exit conditions have been verified, the internal
power-on signal is released to all analog modules.
4. The internal RC oscillator module starts initialization and provides a clock to the system. The PMC
digital interface reset is released after two RC clock cycles.
5. The device proceeds with the reset sequence through RGM phase PHASE0, PHASE1[DEST],
PHASE2[DEST] and PHASE3[DEST].
6. Voltage detector (LVD/HVD) modules are trimmed at the beginning of PHASE3[DEST].
Trimming of the LVDs/HVDs is done by the SSCM at low voltage. After trimming is completed,
the SSCM waits for PMC acknowledge to proceed with the reset sequence.
7. The configurable LVD/HVD modules are optionally enabled at the beginning of PHASE3[DEST]
by programming the PMC_REE/PMC_RES DCF records. After trimming, the PMC interface
monitors all the HVD/LVD outputs that have been enabled by the flash user option bits. When all
enabled LVDs/HVDs are released and the analog temporization period has elapsed, LVDs/HVDs
are unmasked.
8. When the LVDs are masked, the device relies on the PORST signal to detect a voltage failure
during power-up. The device must wait for PORST to be released high before proceeding with
power-up sequence. This may increase the amount of time necessary to complete the reset
sequence.
9. After all LVDs/HVDs are unmasked the SSCM proceeds with the reset sequence, eventually
running full speed accesses to the extended flash option bits required to complete device
configuration.
10. The VDD_HV conditions to exit POWERUP are as follows:
— LVD_HV and LVD_IO upper threshold is crossed
— LVD_VFLASH is crossed
3.7.2 Power-down sequence
During power down, any time the VDD_HV or the VDD_LV supply crosses the respective LVD threshold,
the device enters the POWERUP state. The power-down sequence is entered as soon as the threshold of
one of the LVD_HV, LVD_IO, LVD_core_hot, LVD_VFLASH or POR98 is crossed. The device supplies
may then proceed to drop down to ground either through device leakage or external pull-down.
3.7.3 Brown-out management
During brown-out, the MPC57xx devices re-enter the POWERUP phase as soon as the LVD/HVD
threshold of either VDD_LV or VDD_HV is crossed.
3.7.4 Low voltage during crank
The device is able to continue operation at the minimum input voltage during cranking. In order to proceed
with execution during cranking and prevent device reset, it is important to correctly configure the high
voltage LVDs. Figure 8 illustrates a typical cranking voltage profile.
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