MPC5746R Hardware Design Guide, Rev. 1
Clock Circuitry
NXP Semiconductors20
Figure 8. Example Cranking Voltage Profile
The above diagram shows the input voltage falling to 3.5 V at the battery terminals. Several options are
available to filter the supply sag.
• DC-DC converters to boost the supply
• Additional capacitance to filter the sag
• External power supply system asserts a reset
4 Clock Circuitry
MPC5746R can use either the internal RC oscillator, an external crystal or an external clock as the
reference clock. This reference is qualified by multiple methods before the Phase-Locked Loop (PLL) will
begin lock operation. The ‘pre’ Frequency-Modulated Phase-Locked Loop (FMPLL) circuitry consists of
an automatic level-controlled amplifier, a comparator, a loss of clock detector, and a pre-divider.
Care must be taken in the layout and design of the circuitry around the crystal and FMPLL power supplies.
Any noise in these circuits can affect the accuracy of the clock source to the FMPLL. The PLLs are
powered by VDD_LV. The oscillator (OSC) is powered by VDD_HV_IO_JTAG. Noise on either of these
supplies can affect the accuracy and jitter performance of the oscillator and PLLs.
In order to minimize any potential noise, connect the capacitors recommended in Table 6 to the VDD_LV
and VDD_HV_IO_JTAG supplies.
MPC5746R provides configurable internal load capacitors for the external crystal (Cx and Cy in Figure 9).
This feature is intended to simplify the hardware design and reduce the overall system cost by eliminating
external components and reducing the printed circuit board (PCB) footprint. If an 8 MHz–16 MHz crystal
is used, as shown in Figure 10 external load capacitance must be connected. If the external crystal is to be
started during power-up by hardware, the crystal frequency and the selected load capacitance must be
specified in the UTEST Miscellaneous DCF Client records field. See the MPC5746R Reference Manual
for details.
V
BATT
Time
12 V
5.0 V
3.5 V
t
1
t
2
t
3
t
4
t
5
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