MPC5746R Hardware Design Guide, Rev. 1
Input/Output Pins
NXP Semiconductors24
high at the end of reset PHASE3. Please refer the MPC5746R Reference Manual for more information.
6 Input/Output Pins
The I/O pads are distributed across the I/O supply segments. Each I/O supply segment is associated with
a VDD_HV_IO/VSS_HV supply pair. In order to ensure device reliability, the total current of the I/O on
a single segment should remain below the maximum current per segment value as defined in the data
sheet.
If there is a need to source/sink current through some I/Os, care should be taken to spread the amount of
current between the segments.
In the MPC5746R family, all of the I/Os have a weak pull up/down feature. In addition, input buffers and
the weak-pulls are enabled for all I/Os by default. SD_ADC analog input channels are only multiplexed
with digital inputs.
6.1 I/O Pad Block Diagram (GPIO & Module Multiplexer Port)
The following figure illustrates an I/O pad (without analog inputs) internal block diagram and the
input/output multiplexer. This also illustrates the internal input/output control, pull-up/pull-down control
and module selection. Please refer the system integration unit lite2 (SIUL2) chapter of the MPC5746R
Reference Manual for more information
.
Note: This diagram shows a PAD with full functions. Some Pads do not implement all functions. Refer the MPC5746R reference manual for the details.
Figure 13. I/O pad block diagram without analog inputs
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