Omron CJ1M-CPU21 User Manual

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Auxiliary Area Data Allocation Section 4-3
4-3 Auxiliary Area Data Allocation
4-3-1 Auxiliary Area Flags and Bits for Built-in Inputs
The following tables show the Auxiliary Area words and bits that are related to
the CJ1M CPU Unit's built-in inputs. These allocations apply to CPU Units
equipped with the built-in I/O functions only.
Interrupt Inputs
High-speed Counters
Name Address Description Read/Write Times when data is
accessed
Interrupt Counter 0
Counter SV
A532 Used for interrupt input 0 in counter mode.
Sets the count value at which the interrupt task
will start. Interrupt task 140 will start when inter-
rupt counter 0 has counted this number of
pulses.
Read/Write • Retained when
power is turned
ON.
• Retained when
operation starts.
Interrupt Counter 1
Counter SV
A533 Used for interrupt input 1 in counter mode.
Sets the count value at which the interrupt task
will start. Interrupt task 141 will start when inter-
rupt counter 1 has counted this number of
pulses.
Read/Write
Interrupt Counter 2
Counter SV
A534 Used for interrupt input 2 in counter mode.
Sets the count value at which the interrupt task
will start. Interrupt task 142 will start when inter-
rupt counter 2 has counted this number of
pulses.
Read/Write
Interrupt Counter 3
Counter SV
A535 Used for interrupt input 3 in counter mode.
Sets the count value at which the interrupt task
will start. Interrupt task 143 will start when inter-
rupt counter 3 has counted this number of
pulses.
Read/Write
Interrupt Counter 0
Counter PV
A536 These words contain the interrupt counter PVs
for interrupt inputs operating in counter mode.
In increment mode, the counter PV starts incre-
menting from 0. When the counter PV reaches
the counter SV, the PV is automatically reset to
0.
In decrement mode, the counter PV starts dec-
rementing from the counter SV. When the
counter PV reaches the 0, the PV is automati-
cally reset to the SV.
Read/Write • Retained when
power is turned
ON.
• Cleared when
operation starts.
• Refreshed when
interrupt is gener-
ated.
• Refreshed when
INI(880) instruc-
tion is executed.
Interrupt Counter 1
Counter PV
A537 Read/Write
Interrupt Counter 2
Counter PV
A538 Read/Write
Interrupt Counter 3
Counter PV
A539 Read/Write
Name Address Description Read/Write Times when data is
accessed
High-speed Counter
0 PV
A270 to
A271
Contains the PV of high-speed counter 0. A271
contains the leftmost 4 digits and A270 contains
the rightmost 4 digits.
Read only • Cleared when
power is turned
ON.
• Cleared when
operation starts.
• Refreshed each
cycle during over-
seeing process.
• Refreshed when
PRV(881) instruc-
tion is executed
for the corre-
sponding counter.
High-speed Counter
1 PV
A272 to
A273
Contains the PV of high-speed counter 1. A273
contains the leftmost 4 digits and A272 contains
the rightmost 4 digits.
Read only

Omron CJ1M-CPU21 Specifications

General

Brand	Omron
Model	CJ1M-CPU21
Category	I/O Systems
Language	English