62 /CLDCK O Sub-code frame clock signal output (fCLDCK = 7.35 kHz during normal playback)
63 FCLK O Crystal frame clock signal output (fCLK = 7.35 kHz, double = 14.7 kHz)
64 IPFLAG O Interpolation flag output (“H”: Interpolation)
65 FLAG O Flag output
66 CLVS O Spindle servo phase synchronizing signal output (“H”: CLV, “L”: rough servo)
67 CRC O Sub-code CRC checked output (“H”: OK, “L”: NG)
68 DEMPH O De-emphasis ON signal output(“H”:ON)
69 RESY O Frame re-synchronizing signal output
70 IOSEL I Mode Switching Terminal
71 /TEST I Test input
72 AVDD1 I Power supply input (for analog circuit)
73 OUTL O Left channel audio signal output
74 AVSS1 I GND
75 OUTR O Right channel audio signal output
76 RSEL I RF signal polarity assignment input (at “H” level, RSEL=”H”, at “L” level, RSEL=”L”)
77 IOVOD I 5V supply input
78 PSEL I Test terminal (connected to Gnd)
79 MSEL I SMCK oscillating frequency designation input(“L”:4.2336MHz,“H”:8.4672MHz)
80 SSEL I SUBQ output mode select (“H”: Q-code buffer mode)
● IC703 (BA5948FPE2) Focus Coil/Tracking Coil/Traverse Motor/Spindle Motor Drive
Pin
No.
Mark I/
O
Function
1 IN2 I Motor driver (2) input
2 MUTE2 I Driver mute control input (CH2)
3 IN1 I Motor driver (1) input
4 MUTE1 I Driver mute control input (CH1)
5 NC - Not used
6 NC - Not used
7 NC I Not used
8 NC - Not used
9 PGND1 - Ground connection (1) for driver
10 PVCC1 I Power supply (1) for driver
11 D1- O Motor driver (1) reverse - action output
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