Panasonic SA-PM30MD - Page 30

Pin
No.
Mark I/O Function
24 ECM O Spindle Motor Drive Signal
Output (Forced Mode Output)
25 ECS O Spindle Motor Drive Signal
Output.
(Servo Error Signal Output)
26 KICK O Kick Pulse Output
27 TRD O Tracking Drive Output
28 FOD O Focus Drive Output
29 VREF I D/A (Drive) Output (TVD, ECS,
TRD, FOD, FBAL, TBAL)
Reference Voltage Input
30 FBAL O Focus Error Signal Input
(Analog Input)
31 TBAL O Tracking Balance Adjustment
Output
32 FE I Focus Error Signal Input
(Analog Input)
33 TE I Tracking Error Signal Input
(Analog Input)
34 RFENV I RF Envelope Signal Input
35 VDET I Vibration Detection Signal Input
(“H”: Detect)
36 OFT I Off-Track Signal Input
(“H”: Off Track)
37 TRCRS I Track Cross Signal Input)
38 /RFDET I RF Detection Signal Input
(“L”: Detect)
39 BDO I Dropout Signal Input
(“H”: Dropout)
40 LDON O Laser on Signal Output
(“H”: ON)
41 PLLF2 I/O PLL Loop Filter Characteristic
Switching Terminal
42 TOFS/DSLF2 O Tracking Offset Alignment
Output/ DSL Balance Output
(DA Output)
43 DRF O Double Speed Status Signal
Output
(“H”:DS)
44 ARF I RF Signal Input
45 IREF I Reference Current Input
46 DRF I DSL Bias Terminal
47 DSLF I/O DSL Loop Filter
48 PLLF I/O PLL Loop Filter
49 VCOF I/O VCO Loop Filter Terminal
50 AVDD2 I Power Supply Input (For Analog
Circuit)
51 AVSS2 I GND (For Analog Circuit)
52 EFM O EFM Signal Output (Not Used,
Open)
53 PCK O PLL Extraction Clock Output
(Not Used, Open)
(fPCK= 4.3218 MHz during
Normal Playback)
54 VCOF2 I/O VCO loop Filter for 33.8688
MHz Conversion Terminal for
16.9344 Mhz Crystal mode,
Must use other Circuit)
Pin
No.
Mark I/O Function
1 IN2 I Motor Driver 92) Input
2 PC2 I Turntable Motor Drive Signal
(“L”:ON)
3 IN1 I Motor Driver (1) Input
4 PC1 — Traverse Motor Drive Signal
(“L”:ON)
5 NC — No connection
Pin
No.
Mark I/O Function
55 SUBC O Sub-Code Serial Data Output
(Not Used, Open)
56 SBCK I Clock Input for Sub-Code Serial
Data)
57 VSS I GND
58 X1 IN I Crystal Oscillating Circuit Input
(f= 16.9344 MHz)
59 X2 OUT O Crystal Oscillating Circuit Input
(f= 16.9344 MHz)
60 VDD I Power Supply Input (For
Oscillating Circuit)
61 BYTCK O Byte Clock Output (Not Used,
Open)
62 /CLDCK O Sub-Code Frame Clock Signal
Output
(fCLDCK= 7.35 kHz During
Normal Playback)
63 FCLK O Crystal Frame Clock Signal
Output)
(fCLDCK= 7.35 kHz)
64 IPFLAG O Interpolation Flag Output
(“H”: Interpolation) (Not Used,
Open)
65 FLAG O Flag Output (Not Ised, Open)
66 CLVS O Spindle Servo Phase
Synchronizing Signal Output
(“H”: CLV, “L”: Rough Servo)
(Not used, Open)
67 CRC O Sub-Code CRC Checked
Output
(“H”: OK, “L” NG) (Not Used,
Open)
68 DEMPH O De-Emphasis DN Signal Output
(“H”:ON)
69 RESY O Frame Re-synchronizing Signal
Output
70 IOSEL I Mode Switching Terminal
71 /TEST I Test Input
72 AVDD1 I Power Supply Input (For Analog
Circuit)
73 OUTL O Left Channel Audio Signal
Output
74 AVSS1 I GND
75 OUTR O Right Signal Audio Signal
Output
76 RSEL I RF Signal Polarity Assignment
Input
(at “H” level, RSEL= “H”, at “L”
SEL= “L”)
77 IOVDD I 5V Supply
78 PSEL I Test terminal (Connected to
GND)
79 MSEL I SMCK Oscillating Frequency
Designation Input
(“L”: 4.2336 MHz, “H”
8.4672MHz)
80 SSEL I SUBQ Output Mode Select
(“H”: Q-Code Buffer Mode)
Pin
No.
Mark I/O Function
6 NC — No connection
7 NC — No connection
8 NC — No connection
9 PGND1 — Ground Conenction (1) for Driver
10 PVCC1 I Power Supply (1) for Driver
11 D1- O Motor Driver (1) reverse - action
output
12.8. IC703 (BA5948FPE2) Focus Coil / Tracking Coil / Traverse Motor /
Spindle Motor Driver
30
SA-PM30MD