Pioneer PDP-502MX Service Manual

PDP-502MX, PDP-502MXE
29
A
B
C
D
5
67
8
5
6
7
8
Signal Frequency DET
U-COM
IC2201
( PD2060A )
PLL IC
IC2701
(CXA3106Q)
HD_U
VD_U
HD_PLL
DIGITAL VIDEO ASSY
CLP1
CLP2
HBLK1
VBLK2
ULK_PLL
Serial Control sig
PLD_CE
DATA
CLK
VD_DSEL
SER-->PARA
CONV
HOLD_PLL
DIVOUT
U-COM ASSY
V_STD
Serial data
REQ_Su
HOLD_Su
PLL input HD
HD Freq
Counter
Line
Number
Counter
SYNC STATE
K2030
K2019
K2029
K2018
K2031
K2715
K2702
K2027
HD_DSEL
ADC
IC2401
IC2402
IC2403
( CXA3256R )
ADCK+
ADCK-
RST-
RST+
CLK_AD
K2716
K2419
H_COUNT(0:10)
LINE(0:10)
HOLD signal
generation circuit for
PLL control
Inverted PLL unlock information (Lo: When PLL is not locked)
Clamp & Blanking signal output from
Digital Assy
PLL output HD for A/D sampling &
clock SYNC reference
HOLD controlling signal for comparing
PLL phase comparison.
PLL unlock information
(Hi: When PLL is not locked)
Vertical line number count value (11-bit data)
Data is updated every 1 V sync.
Signal for detecting abnormal SYNC signal (Hi: in detecting)
Count value in the period of 1H by 16MHz clock (11-bit data)
Data is updated at the rate of HD1/8 dividing
Timing signal for capturing horizontal frequency
count value (HD 1/8 dividing)
Vertical SYNC signal for
input signal detection
Signal for detecting vertical frequency limit
Lo: Vertical frequency value is higher than
standard value (In PC input : fixed Hi)
VD SYNC signal sent to Digital Assy
*Input signal detection
(stability)
*No signal input detection
*Detecting vertical frequency
*Controlling V_STD
(detecting frequency value)
Sampling clock for A/D
(differential output)
Reset signal for A/D
(differential output)
Sending
*Data of vertical frequency
*Data of horizontal frequency
*Data of total numbers of lines
*Information on inapplicable
frequency
K2709
K2707
K2706
K2708

Pioneer PDP-502MX Specifications

General

Brand	Pioneer
Model	PDP-502MX
Category	Monitor
Language	English