Quectel LPWA Series Hardware Design

LPWA Module Series
BG950A-GL&BG951A-GL_Hardware_Design
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For BG950A-GL module, pin 27 and pin 28 can only be used as auxiliary UART interface.
Debug UART Interface
Pin Name
Pin No.
I/O
Description
DC
Characteristics
Comment
DBG_RXD
22
DI
Debug UART receive
V
IL
min = -0.2 V
V
IL
max = 0.57 V
V
IH
min = 1.19 V
V
IH
max = 2.0 V
1.8 V power
domain.
If unused, keep
this pin open.
DBG_TXD
23
DO
Debug UART transmit
V
OL
max = 0.38 V
V
OH
min = 1.36 V
Auxiliary/GNSS UART Interface
7
Pin Name
Pin No.
I/O
Description
DC
Characteristics
Comment
AUX/GNSS_TXD
27
DO
Auxiliary/GNSS
UART transmit
V
OL
max = 0.38 V
V
OH
min = 1.36 V
1.8 V power
domain.
If unused, keep
this pin open.
AUX/GNSS_RXD
28
DI
Auxiliary/GNSS
UART receive
V
IL
min = -0.2 V
V
IL
max = 0.57 V
V
IH
min = 1.19 V
V
IH
max = 2.0 V
PCM Interface*
Pin Name
Pin No.
I/O
Description
DC
Characteristics
Comment
PCM_CLK
4
DO
PCM clock
V
OL
max = 0.38 V
V
OH
min = 1.36 V
1.8 V power
domain.
If unused, keep
this pin open.
PCM_SYNC
5
DO
PCM data frame sync
PCM_DIN
6
DI
PCM data input
V
IL
min = -0.2 V
V
IL
max = 0.57 V
V
IH
min = 1.19 V
V
IH
max = 2.0 V
PCM_DOUT
7
DO
PCM data output
V
OL
max = 0.38 V
V
OH
min = 1.36 V
I2C Interface*
Pin Name
Pin No.
I/O
Description
DC
Characteristics
Comment
I2C_SCL
40
OD
I2C serial clock (for
external codec)
External pull-up
resistor is
required.
1.8 V only.
If unused, keep
this pin open.
I2C_SDA
41
OD
I2C serial data (for
external codec)

Quectel LPWA Series Specifications

General

Brand	Quectel
Model	LPWA Series
Category	GSM/GPRS Modules
Language	English