Quectel LPWA Series Hardware Design

LPWA Module Series
BG950A-GL&BG951A-GL_Hardware_Design
25
/89
8
Only BG950A-GL supports GNSS_LNA_EN (pin 51) and VDD_RF (pin 99).
9
It is forbidden to connect high-power loads to VDD_RF, which will cause the system to crash.
level, the module
can enter airplane
mode.
If unused, keep
this pin open.
AP_READY
19
DI
Application processor
sleep state detect
V
IL
min = -0.2 V
V
IL
max = 0.57 V
V
IH
min = 1.19 V
V
IH
max = 2.0 V
1.8 V power
domain.
If unused, keep
this pin open.
PON_TRIG
96
DI
Wake up the module
from PSM
V
IL
min = -0.2 V
V
IL
max = 0.3 V
V
IH
min = 1.2 V
V
IH
max = 2.0 V
1.8 V power
domain.
GRFC Interface*
Pin Name
Pin No.
I/O
Description
DC
Characteristics
Comment
GRFC1
83
DO
Generic RF controller
V
OL
max = 0.38 V
V
OH
min = 1.36 V
V
OH
max = 2.0 V
1.8 V power
domain.
If unused, keep
this pin open.
GRFC2
84
DO
Generic RF controller
External GNSS LNA Interface
8
Pin Name
Pin No.
I/O
Description
DC
Characteristics
Comment
GNSS_LNA_EN
51
DO
External GNSS LNA
enable
V
OL
max = 0.38 V
V
OH
min = 1.36 V
1.8 V power
domain.
If unused, keep
this pin open.
VDD_RF
9
99
PO
Can be used for
external GNSS LNA
power supply
Vnom = 1.9 V
I
O
max = 50 mA
If unused, keep
this pin open.
RESERVED Pins
Pin Name
Pin No.
Comment
RESERVED
11–14, 16, 52, 53, 56, 57, 63, 75, 76, 77, 78, 92–94, 95, 97,
98
Keep these pins
open.
1. For every VBAT transition/re-insertion from 0 V, VBAT slew rate < 25 mV/μs. After the module starts
NOTE

Quectel LPWA Series Specifications

General

Brand	Quectel
Model	LPWA Series
Category	GSM/GPRS Modules
Language	English