Quectel LTE-A Series - Page 24

LTE-A Module Series
EG060V-EA Hardware Design
EG060V-EA_Hardware_Design 23 / 82
SPI Interface
2)
Pin Name
Pin No.
I/O
Description
DC Characteristics
Comment
SPI_CS
166
DO
SPI chip select
V
OL
max = 0.45 V
V
OH
min = 1.35 V
1.8 V power domain.
If unused, keep it open.
SPI_CLK
164
DO
SPI clock
V
OL
max = 0.45 V
V
OH
min = 1.35 V
1.8 V power domain.
If unused, keep it open.
SPI_MOSI
163
DO
SPI master-out
V
OL
max = 0.45 V
V
OH
min = 1.35 V
1.8 V power domain.
If unused, keep it open.
SPI_MISO
165
DI
SPI master-in
V
IL
min = -0.3 V
V
IL
max = 0.6 V
V
IH
min = 1.2 V
V
IH
max = 2.0 V
1.8 V power domain.
If unused, keep it open.
PCIe Interface*
Pin Name
Pin No.
I/O
Description
DC Characteristics
Comment
PCIE_REFCLK_
P
179
AO
PCIe reference
clock (+)
If unused, keep it
open.
PCIE_REFCLK_
M
180
AO
PCIe reference
clock (-)
If unused, keep it
open.
PCIE_TX_M
182
AO
PCIe transmit (-)
If unused, keep it
open.
PCIE_TX_P
183
AO
PCIe receive (+)
If unused, keep it
open.
PCIE_RX_M
185
AI
PCIe receive (-)
If unused, keep it
open.
PCIE_RX_P
186
AI
PCIe receive (+)
If unused, keep it
open.
PCIE_CLKREQ
_N
188
IO
PCIe clock request
V
OL
max = 0.45 V
V
OH
min = 1.35 V
V
IL
min = -0.3 V
V
IL
max = 0.6 V
V
IH
min = 1.2 V
V
IH
max = 2.0 V
In master mode, it is an
input signal.
In slave mode, it is an
output signal.
If unused, keep it
open.
PCIE_RST_N
189
IO
PCIe reset
V
OL
max = 0.45 V
V
OH
min = 1.35 V
V
IL
min = -0.3 V
V
IL
max = 0.6 V
V
IH
min = 1.2 V
V
IH
max = 2.0 V
In master mode, it is an
output signal.
In slave mode, it is an
input signal.
If unused, keep it
open.
PCIE_WAKE_N
190
IO
PCIe wake up
V
OL
max = 0.45 V
V
OH
min = 1.35 V
In master mode, it is an
input signal.