Quectel LTE-A Series User Manual

LTE-A Module Series
EG060V-EA Hardware Design
EG060V-EA_Hardware_Design 50 / 82
In addition, RI behavior can be configured flexibly. The default behavior of RI is shown below.
Table 20: Behavior of RI
The RI behavior can be changed by the AT+QCFG="urc/ri/ring" command. Please refer to document [1]
for details.
3.17. PCIe Interface*
EG060V-EA provides a PCIe interface which is compliant with PCI Express Specification Revision 1.0.
The key features of the PCIe interface are shown below:
⚫ PCI Express Specification Revision 1.0 compliance
⚫ Data rate reaching 2.5 Gbps per lane
⚫ Connection to an external Ethernet IC (MAC and PHY) or WLAN IC.
The following table shows the pin definition of PCIe interface.
Table 21: Pin Definition of PCIe Interface
State
Response
Idle
RI stays at high level
URC
RI outputs 120 ms low pulse when a new URC returns.
Pin Name
Pin No.
I/O
Description
Comment
PCIE_REFCLK_P
179
AO
Output PCIe reference
clock (+)
If unused, keep it open.
PCIE_REFCLK_M
180
AO
Output PCIe reference
clock (-)
If unused, keep it open.
PCIE_TX_M
182
AO
PCIe transmit (-)
If unused, keep it open.
PCIE_TX_P
183
AO
PCIe transmit (+)
If unused, keep it open.
PCIE_RX_M
185
AI
PCIe receive (-)
If unused, keep it open.
PCIE_RX_P
186
AI
PCIe receive (+)
If unused, keep it open.
PCIE_CLKREQ_N
188
IO
PCIe clock request
In master mode, it is an input signal.
In slave mode, it is an output signal.

Quectel LTE-A Series Specifications

General

Brand	Quectel
Model	LTE-A Series
Category	Control Unit
Language	English