LTE-A Module Series
EG060V-EA Hardware Design
EG060V-EA_Hardware_Design 43 / 82
The logic levels are described in the following table.
Table 13: Logic Level Parameters of Digital I/O
The module provides 1.8 V UART interfaces. A level translator should be used if the application is
equipped with a 3.3 V UART interface. A level translator TXS0108EPWR provided by Texas Instruments
is recommended. Below is a reference design.
Figure 21: Reference Design of Translator Chip
Please visit http://www.ti.com for more information on the recommended translator.
Another approach to level translation is with a transistor translation circuit. A reference design in this
regard is shown below. For the design of circuits shown by dotted lines, both input and output circuit
designs, refer to the circuits shown by the solid lines, but please pay attention to the direction of
connection.
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