Quectel SG368Z Series

Smart Module Series
SG368Z_Series_Hardware_Design 70 / 113
⚫ 1 group of 1-lane PCIe 2.0 interface
⚫ Only supports RC mode
⚫ PCIE1_REFCLK_P/M can support both output and input, but they output clock signals for EP device
by default.
⚫ PCIe1 data channel can be multiplexed into SATA2 or QSGMII/SGMII* interface. For detailed
multiplexing relationship, see document [2].
PCIe2 Interface:
⚫ 1 group of 2-lane PCIe 3.0 interface
⚫ Supports PCIe 3.0 × 2 lane RC mode, compatible with PCIe 3.0 × 1 lane RC mode;
PCIe 3.0 × 1 lane RC mode uses PCIE2_TX0_P/M, PCIE2_RX0_P/M channel
⚫ Supports PCIe 3.0 × 2 lane EP mode, compatible with PCIe 3.0 × 1 lane EP mode;
PCIe 3.0 × 1 lane EP mode uses PCIE2_TX0_P/M, PCIE2_RX0_P/M channel
⚫ Supports PCIe 3.0 × 1 lane RC mode + PCIe 3.0 × 1 lane RC mode
⚫ PCIE2_REFCLK_P/M only support input:
Need to provide HCSL level clock input;
Must meet the requirements for PCIe 3.0 clock.
Table 30: Pins Description of PCIe Interfaces
Pin Name
Pin No.
I/O
Description
Comment
PCIE1_TX_P
90
AO
PCIe1 transmit (+)
PCIE1_TX_M
91
AO
PCIe1 transmit (-)
PCIE1_RX_P
86
AI
PCIe1 receive (+)
PCIE1_RX_M
87
AI
PCIe1 receive (-)
PCIE1_REFCLK_P
81
AO
PCIe1 reference clock (+)
PCIE1_REFCLK_M
82
AO
PCIe1 reference clock (-)
PCIE1_CLKREQ_N
366
DI
PCIe1 clock request
PCIE1_WAKE_N
367
DI
PCIe1 wake up
PCIE1_RST_N
333
DO
PCIe1 reset
PCIE2_TX0_P
58
AO
PCIe2 transmit 0 (+)
PCIE2_TX0_M
54
AO
PCIe2 transmit 0 (-)
PCIE2_TX1_P
63
AO
PCIe2 transmit 1 (+)