We can sum up
Z21
's function quite simply: It decodes the
most
significant digit of
the
hex
address. Using
Z21
and the
last two bits, A11
and A10, we can define
any one
of
the
four "memories"
available
to the
CPU
in
BASIC
I.
ADDRESS
DECODER PROGRAMMING
Attached
to the
outputs
of
Z21 is X3. X3 is called
a
"DIP
shunt"
and it is installed in the PCB
position Z3. A DIP
shunt is like
a
shorting bar
array,
except
the
bars may
be
broken. By breaking some bars and
leaving
others intact,
the address decoder is
programmed
to reflect the amount
of RAM or ROM the
CPU
has available for use. In Figure
3,
X3
is
shown with six broken shorting bars. We will
use this
configuration
in
our discussions.
KEYBOARD DECODING
The
keyboard is located from address
3800 to
380F.
The
keyboard is memory, so
RAS*
will be low. A15 is low
because
we are
generating
address codes under
8000.
Look-
ing at our binary location
for the
keyboard,
we
find A14
low,
A13
and
A12
high. With this input combination,
Z21
will be active and pin 12 will be low (Output
3).
Pin 12 is
tied
to
Z36, pin
4. According to the breakdown,
A11
is
high. Z37,
pin
4,
outputs
a
low to Z36, pin 5. The "incor-
rectly drawn" OR
gate
tells
us we need
both
inputs low for
a low output. We
got it, so pin 6 of
Z36
is also low.
Pin
6
of Z36
is tied to pins 12 and
10
of
Z36.
Checking on the
status of A10,
we find
it
listed as being low during a key-
board
address output. Since Z36, pins 12 and 13 are low,
we'll get a low at pin 11.
KYBD*
is generated at
this
pin.
ROM DECODING
When the
CPU
needs instructions
on how to perform a cer-
tain task,
it must access ROM. ROM Decoding
is performed
as
follows: The CPU
needs
a
memory,
so
RAS*
will
go
low.
The
address for
ROM
starts with hex
0,
so
A15, A14, A13,
and A1
2 go
low. Z21
becomes active due
to
the low
at A1
5
and RAS*. Pin
9 of
Z21
goes
low.
Follow pin 9 through the
shorted bar at X3 pins
10
and
7,
past the
pull-up
resistor
R61
and
out
to
ROMA*.
If you find ROMA*
on the
large
schematic, you'll see it goes
to
ROM A, (Z33,
pin 20.)
This
pin
is the CS
(Chip Select) and it is active
low (as
the invert-
ing circle
on pin 20 shows). Z33 turns on, which means
that
its
output
becomes
active
(Note:
the ROM's outputs are
tri-stateable like the buffers.
When
CS
goes low, the ROM
outputs will switch from
a
high
impedance or off-state to
an
on-state. When on, the outputs will
go
low
or high
depending
on the data in the
ROM
at the address specified.)
We got the address applied to ROM A
and we got
ROMA*
to go
low, so ROM A is
turned on.
But
now we need to
insure
a data path is opened so that we can pass data from
ROM
to
CPU.
Notice in
Figure
3,
ROMA* is also attached
to pin 9
of
NAND gate Z74. A
low on
pin 9 will cause
a
resulting high at
pin 8.
Z74,
pin
8,
is
tied
to
Z73,
pin 9.
Z73, pin
8 passes a
high
to
Z74, pin
5. Z74, pin
4,
is tied
to
RD*,
part of the
CPU
control group. Since the
CPU
is
trying
to read data from ROMs, RD* will be low.
Pin
4 of
Z74 will then be high, because RD* is
inverted
by Z52,
pins
13
and
12.
OK, we know pins 4 and 5 of Z74 are high, so
that makes pin 6 low. This low is
MEM*.
If you find MEM*
on the
big
schematic, you will notice it controls
the
ROM/
RAM buffers. The
outputs of the buffers
are
tied
to
the
data
bus.
We now get
ROM
data onto the data bus. Has it
got a way to get to the
CPU? Yes,
it does. Remember that
RD is low because the
CPU
is in a Memory Read cycle.
Since this is so, DBIN* is low and DBOUT*
is high. The
low at DBIN* enables the CPU's input
data
buffers
and
ROM data is available for the CPU.
Finding KYBD*
on the big schematic, you'll see it goes to
the enable inputs of
the data buffers for the keyboard.
The
lower
order address lines
are
tied
to one end
of
the key-
board matrix, while the other
end
of the
matrix is tied to
the
data bus,
through the buffers. If
a
key is pressed, an
address line
will
be "shorted" to a
data line. Assume for
now that this scheme works.
We'll analyze the keyboard
later. The DBOUT*, DBIN* signals are switched
the same
way as if we had
a
ROM select. Therefore,
keyboard data
will
get to the
CPU's
data
bus for processing.
VIDEO
DISPLAY RAM SELECT
In
the binary
breakdown for the memory map,
you will
notice that the binary out for
the video
RAM
address is
almost the same as the keyboard
except for bit A10. Z21,
pin
12,
will output a low to
Z36, pin 4. Since A11 is still
high, Z37, pin
4,
will supply a
low
to
pin
5 of
Z36.
There-
fore, pin
6
of Z36 is low, just as if a
keyboard
was
selected.
Since A10
is
now high, Z36, pin
11,
is high and
KYBD*
is
not active. But
Z36, pin
10
is low and so is pin 9 due to
the
effects of inverter
Z52, pins
1
and 2. Hence,
Z36,
pin
8,
goes low and we
have caused VID*, the Video
RAM select,
to
become active. Assume for now that
VID*
does
select
the video RAMS.
We'll
discuss
what it
does
and how it does
it later.
4K RAM DECODER
As shown
on the memory map, the
address which selects
RAM
extends from hex
4000
to
4FFF
for 4K. The binary
breakdown lists the
states of A15 as a
0,
of course. A14 is
high and A13
and A12 are
low.
We are still accessing
memory, so RAS*
is
low. Hence, Z21
will be active
and
output 4 will
be low (pin
7).
DIP
shunt X3 passes this low
through pins
2 and
15,
and
it
is applied to Z74, pin
10.
It
also is outputted
by the decoder section as RAM*. RAM*
will select the CS
pin on all of the RAMs,
after it passes
through
DIP
shunt X72. (It's
shown on sheet 2 of the large
schematic.)
10
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