Notice that Z53,
pin 1
1
and pin
3,
are also tied to Z37,
pins
2 and 3. Z37,
pin
1,
is an output line
labeled SYSRES*
(System Reset Not). It
is normally-high
and only
goes low
during power
up
(Z53, pin
11,
causes
this), or when
S2 is
pressed (Z53 pin
3,
causes
this). SYSRES*
is used by
the
expansion interface and
is not used
by the TRS-80
in
BASIC I.
One last
thing
to
mention about
these two circuits:
When
you turn off power to the TRS-80
because
of a lost CPU,
wait
at least
10
seconds before
you reapply
power. If
you
do not wait, C42 may not discharge
all the
way and the
CPU
may not
go
back
to address
0000
during a restart.
By
waiting,
C42 will discharge
and
upon
power-up,
the system
will start
at the
correct
ROM location.
WAIT, INT*,
TEST
These
three inputs to the
CPU
are pulled up
to
Vcc
through
resistors.
Since they
are active low, you
may not
have any use for them. But you should know
what they are
for.
The WAIT input, pin 24 of Z40, will slow
the
CPU
down if
there are slow memories it must access. If
this line goes low,
the
CPU will
go
into
a
wait status until
it goes back high.
Once
high, the
CPU continues
with the operation. For
example: Assume you
have
a memory system
that takes
100
microseconds before addressed data can
be guaranteed
to
be present at the output. When
the memory logic sees
that the
CPU
wants
data, it will
make the
WAIT
line low.
At
the end
of
100
microseconds time,
the logic will make
the
WAIT
pin
high, and the
CPU
will
input the data.
The INT (Interrupt Request) is at pin
16
of Z40.
This input
when low, will force the
CPU
into
an
interrupt
request
section of the
memory. It would
then perform some
instruction associated with the interrupt. An example
of
this use
would be
as
follows: Assume
there was a door
on
the back of the TRS-80 that should always be closed. There
was a switch
connected
to the door such that when opened,
the switch contacts are shorted. The switch would be con-
nected to ground and to
pin
16 of
Z40. If
the door were
opened, the
computer
would stop what it was doing and
print on the screen "Close Door." The CPU
would
be inter-
rupted, and it would henpeck you until you closed that
door!
As you can
see,
pin 16 is tied
to
V(X
through a resis-
tor and is not
used. It is, however, used
with the TRS-80
Expansion Interface.
The TEST
input may
be quite useful
in your troubleshoot-
ing.
Pin
25 of
Z40
is labeled
BUSRQ
(Bus Request).
When
this
pin is
brought low, it will force
the data, the address
and the control lines
into
the disabled or floating state.
Although
it is
not used by the TRS-80 in normal operation,
it is
quite
useful when someone wants
to "shut down the
CPU".
We'll
talk about this input
when we discuss the
Control
Logic
Group.
CPU
ADDRESS LINES
There
are system outputs of the microprocessor labeled A0
through A15 that start the address bus. Since
these
lines
must
go to
ROM, RAM, the keyboard
and the video RAM,
they must
be buffered for two reasons. First,
the buffers
must be able to supply
the address bus with
proper logical
levels. The microprocessor cannot supply
the current neces-
sary to drive all of the sections connected
to the address
bus,
and buffers are needed for current
gain. Secondly,
it
may
be necessary to switch off the address
bus. For exam-
ple, if an Expansion Interface is connected
to the bus, it
may be necessary
to
address RAM in
the main unit for
a
data transfer. Therefore, there must
be some method
to
take the CPU off
the data
bus.
The buffers
are tri-state
devices. This
means they will either act
as
buffers
or
as
opened switches.
Z38,
Z39
and part of
Z22
and Z55
are the address line
buffers.
Notice that in Z38
and
Z39
there
are two
sections
of
buffers.
The first
section contains four
buffers and the
second
section contains
only two buffers. Each
section is
controlled by
a single pin. The first
is controlled by pin
1
and the second by
pin 15. When these
control pins are at
a
logical
low, the buffers are enabled
and will operate normal-
ly. When
the control pin is
at a
logical
high, the buffers
are
disabled,
and will show
a
high
impedance from input
to
output. The
signal that controls
the address buffers
is
labeled
"ENABLE*"
and is
sourced at
Z52,
pin 4.
Pin 3
is
the input for control line
inverter, Z52,
and is tied to the
TEST*
line. Notice
that R58 keeps
this
line
pulled high.
Hence,
the address buffers' control line will alwavs
be
at a
logical low; and
therefore,
operating
as
buffers.
If
TEST*
is shorted
to ground, the
address buffers will be disabled.
This
feature could be very useful in
troubleshooting.
CPU
DATA BUS
The
data bus is buffered like the
address bus, except
for
one area. Notice that
there are only eight data lines at the
CPU,
labeled D0 through D7. But
there are 16 buffers.
Remember
that the
CPU must
receive data as well as send
data. The address lines are strictly
CPU
outputs, while the
data
lines are inputs and outputs. Therefore,
there must be
two
sets of buffers
for
the
data
line.
One set handles
CPU
output
data while
the other set takes care of the
CPU
input
data.
The output
data buffers consist of all of Z75
and one
section of Z76. The input buffers
consist of one section of
Z55
and the
last
section of Z76. Notice
that the
input
and
output buffers
are connected "head
to
toe". This could
cause
problems if both
were on at the same time!
The
con-
trol inputs
to the output buffers are all
connected together
on the
line
labeled
DBOUT*, and
are in
turn tied
to
Z53,
pin
6. Likewise, the input buffers' controls
are tied together
on the line
labeled
'DBIN*, and
are connected to
Z53, pin
8.
DBOUT*,
is tied
to
pins 9
and 10
of Z53,
the gate which
generates DBIN*.
6
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