As you can see,
Z53,
pin
6,
is
the major source of input or
output data control.
If pin 6 is high,
DBOUT*
is
high
and
DBIN* is low. Therefore, the input buffers are
enabled and
the
output buffers are disabled.
If Z53, pin
6,
is low,
DBOUT* is low
and
DBIN* is high.
In
this case,
the output
buffers are
enabled and the input buffers are
off.
Pin 4
of
Z53 is tied
to
TEST*. If TEST*
is
grounded, not
only will we disable the address
buffers, but we will also
cause
pin
6 of
Z53
to go
high.
Hence,
the data
output
buffers
will be off, robbing the
CPU's
control
over the data
lines. Since
DBIN*
is now
held low, the input data
buffers
would be active. But, this
would
not
cause any problem
since the address bus from the
CPU
has been
disabled.
When
TEST*
is left alone, it is held
high. If pin 21 of
the
CPU (the Memory Read output) is high, Z53, pin
6,
will
be low.
The low
causes
DBOUT* to be low and
DBIN*
to
be high.
Therefore, the
CPU
is outputting data; and the
buffers are switched accordingly. When pin 21
of Z40 goes
low, Z53,
pin
6,
will be high. We
now have almost the same
condition
as
if TEST* went low.
DBOUT*
is high and
DBIN*
is low but the address
buffers are still enabled.
The
data buffers
arp
now ready for the
CPU
to
accept data.
CPU CONTROL
GROUP
OK, we now
know how the
CPU accesses
the address
bus.
We know the data bus is used
to gather data into the
CPU
or pass data out
of the
CPU.
What we do not know at
this
point is how the
CPU
stores
data in
a
memory or how it
tells the
ROM or RAM that it is ready to
receive
data.
The
CPU control group performs this task.
These signals are:
RD,WR,OUT,
and
IN.
RD (Read)
RD is Read control.
This signal, when activated, will tell
other
sections that the
CPU
is ready
to accept data. RD is
generated at
Z23,
pin 6.
Pin
5
is connected to pin 21 of
Z40,
th e RD (Read)
output.
Pin
4 of Z23 is tied to pin
19,
MREQ (Memory Request), of the
CPU.
Therefore, when
pins
19
and 21 of Z40
go
low at the same time, an
RD out-
put
is generated.
Notice the backward
symbol for an OR
gate.
It's drawn like an AND gate. When we get
MREQ
and RD, then and
only then will we get RD. We're looking
for
two
lows on the input for a low output.
WR (Write)
WR is Write
control. This signal, when activated,
will tell
other sections that the
CPU
is ready to write data into one
of
the memory
locations. WR is generated at
Z23,
pin 11.
Pin
12
of Z23 is
connected to
MREQ. Pin
13 of
Z23 is
tied
to
WR
(Memory Write), which is pin 22 of
Z40. When
we get a low at
the
MREQ
output and a low at the
WR out-
put,
then and only
then will we get
a
low at WR.
OUT (Output)
OUT is Output control. This signal, when activated,
will
enable circuitry
to
perform the cassette save functions.
It
would
also
be used to
control data movement from the
TRS-80
to the
Expansion Interface. OUT
is
generated at
Z23,
pin
3. Pin
1
of Z23 is tied
to
the WR output on the
CPU.
Pin 2 of Z23 is tied to IORQ (Input/Output Request)
which is pin
20
of the
CPU.
When we get a low at
WR and
a low at IORQ, then and only then will
we get a
low
at
OUT.
IN (Input)
IN is Input control. This signal, when activated will
enable
circuitry to
perform
the cassette
load function. It would
also be used
to
control data movement from the
Expansion
Interface to the
TRS-80. IN is
gen
erated
at
Z23,
pin 8.
Pin
10
of Z23 is connected to IORQ.
Pin
9
o
f
Z23
is
tied
to
RD. When we get a
low
at
RD
and a
low
at
IORQ, then and
only then will we get
a
low at IN.
CONTROL GROUP BUS
The
Control
Group must be buffered
for use
by the dif-
ferent sections. Also, the bus may need to be
switched off
at
some time. Therefore, part of Z22 is used to buffer
the
Control Group. Tri-State control
at
pin
1
is tied to the
address
bus control, and
ENABLE*
will affect the status of
the address and the
control
group bus in the same
manner.
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