RL78/G13 CHAPTER 5 CLOCK GENERATOR
R01UH0146EJ0100 Rev.1.00 299
Sep 22, 2011
(7) Operation speed mode control register (OSMC)
This register is used to reduce power consumption by stopping unnecessary clock functions.
If the RTCLPC bit is set to 1, power consumption can be reduced, because clock supply to the peripheral functions,
except the real-time clock and interval timer, is stopped in STOP mode or HALT mode while subsystem clock is
selected as CPU clock. Set bit 7 (RTCEN) of peripheral enable registers 0 (PER0) to 1 before this setting.
In addition, the OSMC register can be used to select the operation clock of the real-time clock and interval timer.
The OSMC register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 5-8. Format of Operation Speed Mode Control Register (OSMC)
Address: F00F3H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
OSMC RTCLPC 0 0
WUTMMCK0
0 0 0 0
RTCLPC Setting in STOP mode or HALT mode while subsystem clock is selected as CPU clock
0 Enables supply of subsystem clock to peripheral functions
(See Table 18-1 for peripheral functions whose operations are enabled.)
1
Stops supply of subsystem clock to peripheral functions other than real-time clock and
interval timer.
WUTMMCK0
Selection of operation clock for real-time clock and interval timer.
0 Subsystem clock (fSUB)
1 Low-speed on-chip oscillator clock (fIL)
Caution The STOP mode current or HALT mode current when the subsystem clock is used can
be reduced by setting the RTCLPC bit to 1. However, no clock can be supplied to the
peripheral functions other than the real-time clock and interval timer during HALT mode
while subsystem clock is selected as CPU clock.
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