Renesas RL78/G1D User Manual

RL78/G13 CHAPTER 8 INTERVAL TIMER
R01UH0146EJ0100 Rev.1.00 458
Sep 22, 2011
8.3 Registers Controlling Interval Timer
The interval timer is controlled by the following registers.
• Peripheral enable register 0 (PER0)
• Operation speed mode control register (OSMC)
• Interval timer control register (ITMC)
(1) Peripheral enable register 0 (PER0)
This register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a
hardware macro that is not used is stopped in order to reduce the power consumption and noise.
When the interval timer is used, be sure to set bit 7 (RTCEN) of this register to 1.
The PER0 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 8-2. Format of Peripheral Enable Register 0 (PER0)
Address: F00F0H After reset: 00H R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
PER0 RTCEN
IICA1EN
Note 1
ADCEN
IICA0EN
Note 2
SAU1EN
Note 3
SAU0EN
TAU1EN
Note 1
TAU0EN
RTCEN Control of real-time clock (RTC) and interval timer input clock supply
0
Stops input clock supply.
• SFR used by the real-time clock (RTC) and interval timer cannot be written.
• The real-time clock (RTC) and interval timer are in the reset status.
1
Enables input clock supply.
• SFR used by the real-time clock (RTC) and interval timer can be read and written.
Notes 1. 80, 100, and 128-pin products only.
2. This is not provided in the 20-pin products.
3. This is not provided in the 20, 24, and 25-pin products.
Cautions 1. When using the interval timer, first set the RTCEN bit to 1, while oscillation of the
input clock (f
RTC) is stable. If RTCEN = 0, writing to a control register of the real-time
clock or interval timer is ignored, and, even if the register is read, only the default
value is read.
2. Clock supply to peripheral functions other than the real-time clock and interval timer
can be stopped in STOP mode or HALT mode when the subsystem clock is used, by
setting the RTCLPC bit of the operation speed mode control register (OSMC) to 1. In
this case, set the RTCEN bit of the PER0 register to 1 and the other bits (bits 0 to 6)
to 0.
3. Be sure to clear the following bits to 0.
20-pin products: bits 1, 3, 4, 6
24, 25-pin products: bits 1, 3, 6
30, 32, 36, 40, 44, 48, 52, 64-pin products: bits 1, 6

Renesas RL78/G1D Specifications

General

Brand	Renesas
Model	RL78/G1D
Category	Computer Hardware
Language	English