Renesas RL78/G1D User Manual

RL78/G13 CHAPTER 6 TIMER ARRAY UNIT
R01UH0146EJ0100 Rev.1.00 376
Sep 22, 2011
(b) Set/reset timing
To realize 0%/100% output at PWM output, the TOmn pin/TOmn bit set timing at master channel timer interrupt
(INTTMmn) generation is delayed by 1 count clock by the slave channel.
If the set condition and reset condition are generated at the same time, a higher priority is given to the latter.
Figure 6-33 shows the set/reset operating statuses where the master/slave channels are set as follows.
Master channel: TOEmn = 1, TOMmn = 0, TOLmn = 0
Slave channel: TOEmp = 1, TOMmp = 1, TOLmp = 0

Renesas RL78/G1D Specifications

General

CPU Core	RL78
Maximum Clock Frequency	32 MHz
Operating Temperature	-40°C to +85°C
Data Flash	4 KB
Pin Count	48
ADC	10-bit, 8 channels
Timers	16-bit Timer: 1 channel, 12-bit Timer: 1 channel, Watchdog Timer: 1 channel
Communication Interfaces	UART, I2C, SPI