RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT
R01UH0146EJ0100 Rev.1.00 568
Sep 22, 2011
(18) Port output mode registers 0, 1, 4, 5, 7 to 9, 14 (POM0, POM1, POM4, POM5, POM7 to POM9, POM14)
These registers set the output mode of ports 0, 1, 4, 5, 7 to 9, and 14 in 1-bit units.
The POM0, POM1, POM4, POM5, POM7 to POM9, and POM14 registers can be set by a 1-bit or 8-bit memory
manipulation instruction.
Reset signal generation clears the POM0, POM1, POM4, POM5, POM7 to POM9, and POM14 registers to 00H.
Figure 12-22. Format of Port Output Mode Registers 0, 1, 4, 5, 7 to 9, and 14 (POM0, POM1, POM4, POM5,
POM7 to POM9, POM14) (128-pin products)
Address F0050H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
POM0 0 0 0 POM04 POM03 POM02 0 POM00
Address F0051H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
POM1 POM17 0 POM15 POM14 POM13 POM12 POM11 POM10
Address F0054H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
POM4 0 0 POM45 POM44 POM43 0 0 0
Address F0055H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
POM5 0 0 POM POM54 POM53 POM52 0 POM50
Address F0057H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
POM7 0 0 0 POM74 0 0 POM71 0
Address F0058H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
POM8 0 0 0 0 0 POM82 POM81 POM 80
Address F0059H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
POM9 0 POM 96 0 0 0 0 0 0
Address F005EH After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
POM14 0 0 0 POM144 POM 143 POM142 0 0
POMmn Pmn pin output buffer selection (m = 0, 1, 4, 5, 7 to 9, 14; n = 0 to 7)
0 Normal output mode
1 N-ch open-drain output (VDD tolerance) mode
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