RL78/G13 CHAPTER 1 OUTLINE
R01UH0146EJ0100 Rev.1.00 43
Sep 22, 2011
(2/2)
80-pin 100-pin 128-pin Item
R5F100Mx R5F101Mx R5F100Px R5F101Px R5F100Sx R5F101Sx
2 2 2 Clock output/buzzer output
• 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz
(Main system clock: f
MAIN = 20 MHz operation)
• 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz
(Subsystem clock: f
SUB = 32.768 kHz operation)
8/10-bit resolution A/D converter 17 channels 20 channels 26 channels
Serial interface [80-pin, 100-pin, 128-pin products]
• CSI: 2 channels/UART: 1 channel/simplified I
2
C: 2 channels
• CSI: 2 channels/UART: 1 channel/simplified I
2
C: 2 channels
• CSI: 2 channels/UART (UART supporting LIN-bus): 1 channel/simplified I
2
C: 2 channels
• CSI: 2 channels/UART: 1 channel/simplified I
2
C: 2 channels
I
2
C bus 2 channel 2 channel 2 channel
Multiplier and divider/multiply-
accumulator
• 16 bits × 16 bits = 32 bits (Unsigned or signed)
• 32 bits ÷ 32 bits = 32 bits (Unsigned)
• 16 bits × 16 bits + 32 bits = 32 bits (Unsigned or signed)
DMA controller 4 channels
Internal 37 37 41
Vectored interrupt
sources
External 13 13 13
Key interrupt 8 8 8
Reset
• Reset by RESET pin
• Internal reset by watchdog timer
• Internal reset by power-on-reset
• Internal reset by voltage detector
• Internal reset by illegal instruction execution
Note
• Internal reset by RAM parity error
• Internal reset by illegal-memory access
Power-on-reset circuit
• Power-on-reset: 1.51 ±0.03 V
• Power-down-reset: 1.50 ±0.03 V
Voltage detector 1.63 V to 4.06 V (14 stages)
On-chip debug function Provided
Power supply voltage VDD = 1.6 to 5.5 V
Operating ambient temperature TA = −40 to +85 °C
Note The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip debug
emulator.
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