RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT
R01UH0146EJ0100 Rev.1.00 603
Sep 22, 2011
(4) Processing flow (in continuous transmission/reception mode)
Figure 12-48. Timing Chart of Master Transmission/Reception (in Continuous Transmission/Reception Mode)
(Type 1: DAPmn = 0, CKPmn = 0)
SSmn
SEmn
SDRmn
SCKp pin
SIp pin
Shift
register mn
INTCSIp
TSFmn
SOp pin
Reception & shift operation
Reception & shift operation
BFFmn
Reception & shift operation
MDmn0
Data transmission/reception (8-bit length)
Data transmission/reception (8-bit length)
Data transmission/reception (8-bit length)
STmn
<4> <5>
Transmit data 1 Transmit data 3
Receive data 3
Write
Read
Read
Read
Write
<1>
<2>
<3>
<2>
<3>
<4> <2>
<7> <8>
(Note 1)
Transmit data 2
Write
<6>
<3>
(Note 2)
(Note 2)
Receive data 2
Receive data 1
Receive data 1
Receive data 2
Receive data 3
Transmit data 3
Transmit data 2
Transmit data 1
Notes 1. If transmit data is written to the SDRmn register while the BFFmn bit of serial status register mn
(SSRmn) is 1 (valid data is stored in serial data register mn (SDRmn)), the transmit data is overwritten.
2. The transmit data can be read by reading the SDRmn register during this period. At this time, the
transfer operation is not affected.
Caution The MDmn0 bit of serial mode register mn (SMRmn) can be rewritten even during operation.
However, rewrite it before transfer of the last bit is started, so that it has been rewritten before the
transfer end interrupt of the last transmit data.
Remarks 1. <1> to <8> in the figure correspond to <1> to <8> in Figure 12-49 Flowchart of Master
Transmission/Reception (in Continuous Transmission/Reception Mode).
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 10, 11, 20, 21,
30, 31), mn = 00 to 03, 10 to 13
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