RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA
R01UH0146EJ0100 Rev.1.00 721
Sep 22, 2011
Caution Note the minimum fCLK operation frequency when setting the transfer clock. The minimum fCLK
operation frequency for serial interface IICA is determined according to the mode.
Fast mode: f
CLK = 3.5 MHz (MIN.)
Fast mode plus: f
CLK = 10 MHz (MIN.)
Normal mode: fCLK = 1 MHz (MIN.)
In addition, the fastest operation frequency of the operation clock of the serial interface IICA is 20
MHz (Max.). If the f
CLK exceeds 20 MHz, set the clock to fCLK/2 by setting the PRS0 bit of IICCTL01
register to 1.
Remarks 1. Calculate the rise time (t
R) and fall time (tF) of the SDAA0 and SCLA0 signals separately, because
they differ depending on the pull-up resistance and wire load.
2. IICWL0: IICA low-level width setting register 0
IICWH0: IICA high-level width setting register 0
t
F: SDAA0 and SCLA0 signal falling times
t
R: SDAA0 and SCLA0 signal rising times
f
CLK: CPU/peripheral hardware clock frequency
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