RL78/G13 CHAPTER 15 DMA CONTROLLER
R01UH0146EJ0100 Rev.1.00 802
Sep 22, 2011
(2) DMA RAM address register n (DRAn)
This is a 16-bit register that is used to set a RAM address that is the transfer source or destination of DMA
channel n.
Addresses of the internal RAM area other than the general-purpose registers (see table 15-2) can be set to this
register.
Set the lower 16 bits of the RAM address.
This register is automatically incremented when DMA transfer has been started. It is incremented by +1 in the 8-
bit transfer mode and by +2 in the 16-bit transfer mode. DMA transfer is started from the address set to this
DRAn register. When the data of the last address has been transferred, the DRAn register stops with the value of
the last address +1 in the 8-bit transfer mode, and the last address +2 in the 16-bit transfer mode.
In the 16-bit transfer mode, the least significant bit is ignored and is treated as an even address.
The DRAn register can be read or written in 8-bit or 16-bit units. However, it cannot be written during DMA
transfer.
Reset signal generation clears this register to 0000H.
Figure 15-2. Format of DMA RAM Address Register n (DRAn)
Address: FFFB2H, FFFB3H (DRA0), FFFB4H, FFFB5H (DRA1) , After reset: 0000H R/W
F0202H, F0203H (DRA2), F0204H, F0205H (DRA3)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DRAn
(n = 0 to 3)
Table 15-2 Internal RAM Area other than the General-purpose Registers
Part Number Internal RAM Area other than the General-purpose Registers
R5F100xA, R5F101xA (x = 6 to 8, A to C, E to G),
R5F100xC, R5F101xC (x = 6 to 8, A to C, E to G, J, L)
FF700H to FFEDFH
R5F100xD, R5F101xD (x = 6 to 8, A to C, E to G, J, L) FF300H to FFEDFH
R5F100xE, R5F101xE (x = 6 to 8, A to C, E to G, J, L) FEF00H to FFEDFH
R5F100xF, R5F101xF (x = A to C, E to G, J, L, M, P) FDF00H to FFEDFH
R5F100xG, R5F101xG (x = A to C, E to G, J, L, M, P) FCF00H to FFEDFH
R5F100xH, R5F101xH (x = E to G, J, L, M, P, S) FBF00H to FFEDFH
R5F100xJ, R5F101xJ (x = F, G, J, L, M, P, S) FAF00H to FFEDFH
R5F100xK, R5F101xK (x = F, G, J, L, M, P, S) F9F00H to FFEDFH
R5F100xL, R5F101xL (x = F, G, J, L, M, P, S) F7F00H to FFEDFH
Remark n: DMA channel number (n = 0 to 3)
DRA0H: FFFB3H
DRA1H: FFFB5H
DRA2H: F0203H
DRA3H: F0205H
DRA0L: FFFB2H
DRA1L: FFFB4H
DRA2L: F0202H
DRA3L: F0204H
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