RL78/G13 CHAPTER 18 STANDBY FUNCTION
R01UH0146EJ0100 Rev.1.00 866
Sep 22, 2011
(b) Release by reset signal generation
When the reset signal is generated, STOP mode is released, and then, as in the case with a normal reset
operation, the program is executed after branching to the reset vector address.
Figure 18-6. STOP Mode Release by Reset
(1) When high-speed system clock is used as CPU clock
STOP
instruction
Reset signal
High-speed
system clock
(X1 oscillation)
Normal operation
(high-speed
system clock)
STOP mode
Reset
period
Normal operation
(high-speed on-chip
oscillator clock)
Oscillates
Oscillation
stopped
Oscillates
Status of CPU
Oscillation stabilization time
(Check by using OSTC register)
Oscillation
stopped
Starting X1 oscillation is
specified by software.
Oscillation stopped
Reset processing
Note
(2) When high-speed on-chip oscillator clock is used as CPU clock
STOP
instruction
Reset signal
High-speed on-chip
oscillator clock
Normal operation
(high-speed on-chip
oscillator clock)
STOP mode
Reset
period
Normal operation
(high-speed on-chip
oscillator clock)
Oscillates
Oscillation
stopped
Status of CPU
Oscillates
Oscillation stopped
Wait for oscillation
accuracy stabilization
Reset processing
Note
Note Reset processing time: 387 to 720
μ
s (When LVD is used)
155 to 407
μ
s (When LVD off)
Remark f
X: X1 clock oscillation frequency
<R>
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