Renesas RL78/G1D User Manual

RL78/G13 CHAPTER 28 INSTRUCTION SET
R01UH0146EJ0100 Rev.1.00 975
Sep 22, 2011
Table 28-5. Operation List (14/17)
Notes 1. Number of CPU clocks (f
CLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or
when no data is accessed
2. Number of CPU clocks (f
CLK) when the program memory area is accessed.
Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction
from the internal RAM area, the number becomes double number plus 3 clocks at a maximum.
Clocks Flag
Instruction
Group
Mnemonic Operands Bytes
Note 1 Note 2
Clocks
Z AC CY
CY, A.bit 2 1
−
CY ← CY ∨ A.bit ×
CY, PSW.bit 3 1
−
CY ← CY ∨ PSW.bit ×
CY, saddr.bit 3 1
−
CY ← CY ∨ (saddr).bit ×
CY, sfr.bit 3 1
−
CY ← CY ∨ sfr.bit ×
CY, [HL].bit 2 1 4 CY ← CY ∨ (HL).bit ×
XOR1
CY, ES:[HL].bit 3 2 5 CY ← CY ∨
(ES, HL).bit ×
A.bit 2 1
−
A.bit ← 1
PSW.bit 3 4
−
PSW.bit ← 1 × × ×
!addr16.bit 4 2
−
(addr16).bit ← 1
ES:!addr16.bit 5 3
−
(ES, addr16).bit ← 1
saddr.bit 3 2
−
(saddr).bit ← 1
sfr.bit 3 2
−
sfr.bit ← 1
[HL].bit 2 2
−
(HL).bit ← 1
SET1
ES:[HL].bit 3 3
−
(ES, HL).bit ← 1
A.bit 2 1
−
A.bit ← 0
PSW.bit 3 4
−
PSW.bit ← 0 × × ×
!addr16.bit 4 2
−
(addr16).bit ← 0
ES:!addr16.bit 5 3
−
(ES, addr16).bit ← 0
saddr.bit 3 2
−
(saddr.bit) ← 0
sfr.bit 3 2
−
sfr.bit ← 0
[HL].bit 2 2
−
(HL).bit ← 0
CLR1
ES:[HL].bit 3 3
−
(ES, HL).bit ← 0
SET1 CY 2 1
−
CY ← 1 1
CLR1 CY 2 1
−
CY ← 0 0
Bit
manipulate
NOT1 CY 2 1
−
CY ← CY ×

Renesas RL78/G1D Specifications

General

Brand	Renesas
Model	RL78/G1D
Category	Computer Hardware
Language	English