Sel SEL-421 - Page 28

xxx List of Figures
SEL-421/SEL-421-1 Relay Date Code 20020501
Figure 1.38 Phase Instantaneous and Directional Overcurrent............................................................ R.1.66
Figure 1.39 Residual Ground Instantaneous and Directional Overcurrent. ......................................... R.1.67
Figure 1.40 Negative-Sequence Instantaneous and Directional Overcurrent. ..................................... R.1.68
Figure 1.41 US Moderately Inverse—U1. ........................................................................................... R.1.74
Figure 1.42 US Inverse—U2. .............................................................................................................. R.1.75
Figure 1.43 US Very Inverse—U3. ...................................................................................................... R.1.76
Figure 1.44 US Extremely Inverse—U4.............................................................................................. R.1.77
Figure 1.45 US Short-Time Inverse—U5. ........................................................................................... R.1.78
Figure 1.46 IEC Standard Inverse—C1. .............................................................................................. R.1.79
Figure 1.47 IEC Very Inverse—C2...................................................................................................... R.1.80
Figure 1.48 IEC Extremely Inverse—C3............................................................................................. R.1.81
Figure 1.49 IEC Long-Time Inverse—C4. .......................................................................................... R.1.82
Figure 1.50 IEC Short-Time Inverse—C5. .......................................................................................... R.1.83
Figure 1.51 Selectable Time-Overcurrent Element Logic Diagram. ................................................... R.1.84
Figure 1.52 SOTF Logic Diagram. ...................................................................................................... R.1.87
Figure 1.53 Required Zone Directional Settings. ................................................................................ R.1.88
Figure 1.54 DCB Logic Diagram......................................................................................................... R.1.92
Figure 1.55 Permissive Trip Receiver Logic Diagram. ....................................................................... R.1.96
Figure 1.56 POTT Logic Diagram. ...................................................................................................... R.1.97
Figure 1.57 POTT Cross-Country Logic Diagram. ............................................................................. R.1.98
Figure 1.58 Permissive Trip Receiver Logic Diagram. ..................................................................... R.1.101
Figure 1.59 DCUB Logic Diagram.................................................................................................... R.1.102
Figure 1.60 Trip Logic Diagram. ....................................................................................................... R.1.108
Figure 1.61 Two Circuit Breakers Trip Logic Diagram..................................................................... R.1.110
Figure 1.62 Trip A Unlatch Logic...................................................................................................... R.1.111
Figure 1.63 Trip During Pole Open. .................................................................................................. R.1.111
Figure 1.64 Scheme 1 Logic Diagram. .............................................................................................. R.1.113
Figure 1.65 Scheme 2 Three-Pole Circuit Breaker Failure Protection Logic.................................... R.1.114
Figure 1.66 Scheme 2 Single-Pole Circuit Breaker Failure Protection Logic. .................................. R.1.114
Figure 1.67 Current-Supervised Three-Pole Retrip Logic................................................................. R.1.115
Figure 1.68 Current-Supervised Single-Pole Retrip Logic................................................................ R.1.115
Figure 1.69 No Current/Residual Current Circuit Breaker Failure Protection Logic Diagram......... R.1.116
Figure 1.70 Circuit Breaker Failure Seal-In Logic Diagram. ............................................................ R.1.121
Figure 1.71 Failure to Interrupt Load Current Logic Diagram. ......................................................... R.1.121
Figure 1.72 Flashover Protection Logic Diagram.............................................................................. R.1.122
Figure 1.73 Circuit Breaker Failure Trip Logic Diagram. ................................................................. R.1.122
Section 2: Auto-Reclose and Synchronism Check
Figure 2.1 Auto-Reclose State Diagram for Circuit Breaker 1............................................................ R.2.4
Figure 2.2 Multiple Circuit Breaker Arrangement............................................................................. R.2.15
Figure 2.3 Multiple Circuit Breaker Arrangement............................................................................. R.2.18
Figure 2.4 Leader/Follower Selection by Relay Input....................................................................... R.2.22
Figure 2.5 Voltage Sources for Circuit Breaker-and-a-Half Arrangement. ....................................... R.2.27
Figure 2.6 Voltage Sources for Single Circuit Breaker Arrangement................................................ R.2.27
Figure 2.7 Voltage Sources for Single Circuit Breaker Arrangement................................................ R.2.28
Figure 2.8 Circuit Breaker Pole-Open Logic Diagram. ..................................................................... R.2.32
Figure 2.9 Line-Open Logic Diagram................................................................................................ R.2.32
Figure 2.10 Single-Pole Reclose Enable.............................................................................................. R.2.33
Figure 2.11 Three-Pole Reclose Enable............................................................................................... R.2.33
Figure 2.12 Voltage Check Elements. .................................................................................................. R.2.33
Figure 2.13 One Circuit Breaker Single-Pole Cycle State (79CY1).................................................... R.2.34
Figure 2.14 One Circuit Breaker Three-Pole Cycle State (79CY3)..................................................... R.2.35
Figure 2.15 Two Circuit Breakers Single-Pole Cycle State (79CY1).................................................. R.2.36
Figure 2.16 Two Circuit Breakers Three-Pole Cycle State (79CY3)................................................... R.2.38
Figure 2.17 Partial Breaker-and-a-Half or Partial Ring-Bus Breaker Arrangement............................ R.2.41
Figure 2.18 Voltage Angle Difference in a Paralleled System............................................................. R.2.42
Figure 2.19 Synchronism-Check Voltages for Two Circuit Breakers.................................................. R.2.43
Figure 2.20 Synchronism-Check Settings............................................................................................ R.2.44