– 83 –
MD-C2
IC2 VHiLC78622N-1: Servo/Signal Control (LC78622NE) (2/2)
Pin No.
Function
Terminal Name
Input/Output
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
51 SBCK Input Clock input terminal to read subcode. Schmit input.
52* FSX Output Output terminal of synchronous signal of 7.35kHz divided from quartz oscillation.
53 WRQ Output Output terminal to stand by output of subcode Q.
54 RWC Input Input terminal of read/write. Schmit input.
55 SQOUT Output Output terminal of subcode Q.
56 COIN Input Command input terminal from microcomputer.
57 *CQCK Input Clock input terminal to fetch command input, or pick up subcode from SQOUT. Schmit input.
58 *RES Input Reset input terminal of LC78622. When turning on power, set it at "L".
59* TST11 Output Output terminal for test. Used in the open state ( "L" output as ordinary).
60* 16M Output Output terminal of 16.9344MHz.
61 4.2M Output Output terminal of 4.2336Hz.
62 TEST5 Input Input terminal for test. Pull-down resistor is integrated.
63 *CS Input Chip selection input terminal. Pull-down resistor is integrated.
64 TEST1 Input Input terminal for test. Pull-down resistor is integrated.
TOFF
TGL
JP+
JP–
PCK
FSEQ
V
DD
CONT1
CONT2
CONT3
CONT4
CONT5
EMPH/CONT6
C2F
DOUT
TEST3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DEFI
TAI
PDO
VVss
ISET
VV
DD
FR
Vss
EFMO
EFMIN
TEST2
CLV+
CLV–
V/
*
P
HFL
TES
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
EFLG
SBSY
XVss
XIN
XOUT
XV
DD
MUTER/CONT8
RV
DD
RCHO
RVss
LVss
LCHO
LV
DD
MUTEL/CONT7
PCCL
TEST4
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
TEST1
*
CS
TEST5
4.2M
16M
TST11
*
RES
*
CQCK
COIN
SQOUT
RWC
WRQ
FSX
SBCK
SFSY
PW
DEFI
EFMIN
FSEQ
V/P
PW
SBCK
SBSY
SFSY
CS
WRQ
SQOUT
COIN
RWC
CQCK
HLF
TES
TOFF
JP-
JP+
RES
TGL
CONT1
CONT2
CONT3
CONT4
CONT5
EMPH
EFLG
16M
4.2M
XVss
FSX
XIN
XOUT
XV
DD
RVss
RV
DD
MUTER
RCHO
LCHO
MUTEL
LVss
LV
DD
(NC)
DOUT
C2F
EFMO
VV
DD
VVss
PDO
I SET
FR
PCK
TAI
TSTI1
TEST1
TEST2
TEST3
TEST4
TEST5
V
DD
Vss
CLV+
CLV-
Slice level
control
VCO colck oscillation
clock control
2 Kx
8bit
RAM
RAM address
generator
Interpolation mute
Bilingual
Digital OUT
Digital
attenuator
X4 oversampling
digital filter
1bitDAC
L.P.F
XTAL system timing
generator
General-use port
Servo commander
µ COM
Interface
Subcode division
QCRC
CLV
Digital servo
Sync detection
EFM demodulation
Flag processing of C1/C2
error detection and correction
Figure 83 BLOCK DIAGRAM OF IC
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