Sharp MZ-5500 - Page 104

°VDCl, VDCZ
The VDC1 is the LSI which generates various timings and the VDC2
synthesizes display signal. Internal registers uf these chips are write
permitted.
°Resolutiun select register (1/0 address 130H)
DZ Dl DO
~ 00: When HZIDI3, MZ1D14, or HDIDl~ is used
(400-raster).
01: When other than MZID13, MZIDI4, and MZID18 is
I
used (ZOO-raster).
10: For superimpose
11: When MZ1D13 or HZID14, or MDID18 is used.
L- ________ ~, 0: Wh cn horizontal dot mode is 640 dots.
l: \-lhen horizontal dot mode is 320 dots.
The resolution must be selected using the SYNC command of the GDC and thp.
address 130H.
°Mode
select register (1/0 address lZ0H)
DZ Dl DO
I x I I
I
>0: Color mode
1: Monochrome mode
[
0: Don't care
--------~,O: Normal color display
1: Plane preference mode
f
NOTE:
DZ must be programmed 0 in the case Qf the monocprome mode.
As the block diagram uf th ,e VDC2 is shown in Fig.lS-l0, DO ()f the address
120H is the select signal for the last selector. Since plane s , 0 - 2, are
ANDed with VDSO - 2, it has to be determined in the monochrome mode with
which plane should it be ORed to display.
10 \