Sharp MZ-5500 - Page 114

Command
1
(
12
14 WAIT
15 FINIT
16 WAIT
17 FILD
(BX]
18 WAIT
19 FIADD
DS: [BX]
20 WAIT
8086
8087
Memory address
Commands fetched are all
1 to 20000H. disregarded.
2 to 20002H.
o to 20004H.
Test pin is checked. At not busy state.
Advances to a next step, WAIT command disregarded.
if 0 (8087 being not busy).
Disregarded as it is a NDP Executes the same function as
cornmand. hardware resel.
Similsr as 14, it waits In busy state while the reset
until the 8087 turns not is being carried out.
busy (8 clocks at a
t
maximum).
The
EU does nothing as it The address 1s stored in the
is a NDP command. Because data pointer inside the NUP
the NDP needs to refer the -) during the dummy cyclp. the CPU
memory, th~ BIU creates the
physical address from DS
executes ..
J,
and BX and ' dummy read cycle RQ pulse i8 issued
tu the epu
is execu ted. / to reques t f or the
bus
~ privilege ·.
Upon
receiving of RQ, GT Memory read cycle is executed
pulse is sent out to
from the address implied by the
release the bus for use, ~ data pointer to rush the data
if satisfactory.
in ST(O). The data in ST(n) i8
stored in ST(n+l), then.
An integer type da ta are ~ *lf the command i8 the long re<1]
automatically converted load command, four memory
into the real type cycles are needed.
temporarily and stored.
1
Goes into a next bus cycle. ~ Release pulse is returned to the
CPU to 6pen the bus free.
Similar as 14. Similar as 14.
Similar as 17. Though similar as 17, addition
of ST(O) with the data is stored
in ST(O), instead of storing the
data in ST(O).
Similar as 14.
Similar as 14.
l I \