Sharp MZ-5500 - Page 32

(2) PIC mask register clear
Since the IR-26 has been masked initially, it does not permit to accept
the interrupt unless the mask register is cleared.
PIC mask register 1/0 address: Master PIC ... 32H
Slave PIC .... 42H
The IR-26 should be programmed as foliows;
IN AL, 42H
AND AL, OBFH
OUT 42H, AL
(3) EOI generation
At the termination of the interrupt routine, there is a need of informjng
the end of the interrupt processing to the PICo
MOV AL, 20H
OUT 40H, AL
OUT 30H, AL
IRET
Example:
CSEG
ORG lOOH
XOR
BX, EX
1 Programming the
MOV BS, BX
interrupt address
MOV
BX, lOOH+4*14
MOV
AX, OFFSET INT26
MOV
[BX], AX
INC
BX
INC
BX
MOV
[BX], CS
PUSH CS
J Assign the 8080 model
POP
DS
I
CLI
IN
AL, 42H
J Clear the mask register
AND AL, OBFH
OUT
42H, AL
STI
1 Interrupt enabled
INT26: MOV DX, IBOH
J Interrupt acknowledge
OUT
DX, AL
MOVE
AL, 20H
J EOI generated
OUT
40H, AL
OUT
30H, AL
IRET
2~