Sharp UP-600

15. TCP/IP STACK
The LAN of the UP-600 uses as the protocol Ethernet, which supports
TCP/IP.
The interface with the TCP/IP board is achieved through 2 interrupt
signals and dual-port RAM.
The decode of dual-port RAM is located in the following space:
DP-RAM: F20000H - F2FFFFH (max. 64 KB)
The interruption from the TCP/IP is allocated as follows:
EXINTO: INTSW (SLAVE WRITE interrupt) bit 6 of 00FF81H
EXINT1: INTSR (SLAVE READ interrupt) bit 0 of 00FF80H
<TCP/IP connector terminals>
Signal Name Pin No. Pin No. Signal Name
+5V 2 1 +5V
+5V 4 3 +5V
A14 6 5 A15
A12 8 7 A13
HWR 10 9 DPCS
A10 12 11 A11
A0 14 13
RD
A2 16 15 A1
A4 18 17 A3
A6 20 19 A5
A8 22 21 A7
D7 24 23 A9
D5 26 25 D6
D3 28 27 D4
D1 30 29 D2
LRES 32 31 D0
INTSW 34 33 INTSR
-3635-
GND 38 37 GND
GND 40 39 GND
16. RS232
Two standard RS232 channels are compatible with the ER-A5RS.
However, while the ER-A5RS uses the
IRQ2 terminal of the CPU for
interruption of the RS232, the UP-600 cannot use the
IRQ1 terminal
instead of it. (The
IRQ2 terminal is used for IR as the SCK1 terminal.)
The standard RS232 is fixed to the logic channels 1 and 8. Use the
channels 2, 3, 4, 5, 6 and 7 for the ER-A5RS.
17. MCR
This paragraph describes the MCR option (UP-E13MR) control de-
fined by the UP-600 hardware architecture.
3 channels of the serial port (interchangeable with 8251) built in the
MPCA9 are used. 3 tracks of data are read simultaneously. (UP-
E13MR)
1) CPU INTERFACE
The CPU interface for the USART (8251) and magnetic card reader
(MCM-21) in the UP-600 system is shown below.
Signal description
RCP1 TRACK 1 CLOCK PULSE
RDD1 TRACK 1 DATA SIGNAL
RCP2 TRACK 2 CLOCK PULSE
RDD2 TRACK 2 DATA SIGNAL
RCP3 TRACK 3 CLOCK PULSE
RCD3 TRACK 3 DATA SIGNAL
CLS1 TRACK 1 CARD DETECTION SIGNAL
CLS2 TRACK 2 CARD DETECTION SIGNAL
CLS3 TRACK 3 CARD DETECTION SIGNAL
RCVRDY1 TRACK 1 DATA RECEIVING SIGNAL
RCVRDY2 TRACK 2 DATA RECEIVING SIGNAL
RCVRDY3 TRACK 3 DATA RECEIVING SIGNAL
INTMCR INTERRUPT SIGNAL OR-SYNTHESIZED from
RCVRDY and SYNC input
2 chip select signals for the 8251 are generated inside MPCA8.
2) MCR INTERFACE
The operating timing of the MCR interface signals is given below.
(1) Example of timing
(2) Detailed timing (relation between DATA and CLOCK PULSE)
The "NULL" CODE is basically written prior to the opening code. The
opening code detection algorithm is considered because data may
become corrupt before and after the CARD detection signal due to a
worn magnet stripe.
CPU
ICI
INTMCR
RCVRDY1
RCVCLK2
RDD1
RCP2
RDD2
CLS1
RCVDT1
RCP1
/DSR1
CLS2
RCVDT2
8251
x 2
Integrated as MPCA8
in the UP-600 system.
RCVCLK1
/DSR2
CLS1,
CLS2
RCVRDY1
RCVRDY2
INTMCR
SYNC
MPCA7
RCP1
CLS2
RCVRDY3
RCVRDY2
RDD3
RCVDT3
/DSR3
RCVCLK3
CLS3
RCP3
RDD1/RDD2
RCP1/RCP2
CLS1/CLS2
RDD3
RCP3
CLS3
"0" "1" "1"
Approx. 16µs
Min.
5
µs
RDD1/RDD2
RCP1/RCP2
RDD3
RCP3