Counting operating mode (CNT)
4.2 Parameters/address space
Digital input module DI 8x24VDC HS (6ES7131‑6BF00‑0DA0)
42 Manual, 03/2015, A5E35243810-AA
Notes on the feedback bits
This bit indicates the status of the respective digital input DI
n
.
COUNT_VALUE This value returns the current counter value for the respective channel.
STS_DQ This bit depends on the "Set output" parameter of the respective channel. You can use
STS_DQ in each case, in order to control a digital output module's digital output.
STS_GATE Together, the software gate and the hardware gate form the internal gate. This bit indicates
the status of the internal gate for the respective channel. The module only counts if the in-
ternal gate is open.
0 means: Gate closed
1 means: Gate open
Note:
If you change a channel parameter in RUN mode via data record 128, all of the changed
channel's values are retransferred to the module. In doing so, the internal gate of the re-
spective channel is closed and the counter value is set to the start value. To restart count-
ing, you need to close and reopen the software gate in each case.
LD_STS_SLOT This bit indicates for the respective channel, by mean of a status change (toggling), that the
load request for SLOT (LD_SLOT) has been detected and executed.
LD_ERROR This bit indicates for the respective channel that an error occurred (latching) during loading
via the control interface. The loaded value was not applied. One of the following conditions
has not been met:
• Counter low limit ≤ counter value
(If this condition is not met, the start value is loaded as the current counter value.)
• Counter low limit ≤ start value
• Counter low limit ≤ comparison value 0/1
• Counter high limit ≥ counter value
(If this condition is not met, the start value is loaded as the current counter value.)
• Counter high limit ≥ start value
• Counter high limit ≥ comparison value 0/1
• Counter low limit < counter high limit
• Comparison value 0 < comparison value 1
• Do not write a reserved load request in LD_SLOT
EVENT_UFLW For the respective channel, this bit indicates the saved state which shows that there was a
counter value underflow (a violation of the counter low limit). You reset the status by ac-
knowledgment with RES_EVENT_UFLW.
EVENT_OFLW For the respective channel, this bit indicates the saved state which shows that there was a
counter value overflow (a violation of the counter high limit). You reset the status by ac-
knowledgment with RES_EVENT_OFLW.
EVENT_CMP0 For the respective channel, this bit indicates the saved status which shows that a compari-
son event with comparison value 0 has occurred. You reset the status by acknowledgment
with RES_EVENT_CMP0.
The EVENT_CMP0 bit is not set when you set the counter value to the start value.
EVENT_CMP1 For the respective channel, this bit indicates the saved status which shows that a compari-
son event with comparison value 1 has occurred. You reset the status by acknowledgment
with RES_EVENT_CMP1.
The EVENT_CMP1 bit is not set when you set the counter value to the start value.
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