Counting operating mode (CNT)
4.2 Parameters/address space
Digital input module DI 8x24VDC HS (6ES7131‑6BF00‑0DA0)
Manual, 03/2015, A5E35243810-AA
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RES_EVENT_UFLW_ACK This bit indicates for the respective channel that the reset of event bit EVENT_UFLW is
RES_EVENT_OFLW_ACK This bit indicates for the respective channel that the reset of event bit EVENT_OFLW is
active.
RES_EVENT_CMP0_ACK This bit indicates for the respective channel that the reset of event bit EVENT_CMP0 is
RES_EVENT_CMP1_ACK This bit indicates for the respective channel that the reset of event bit EVENT_CMP1 is
Complete acknowledgment principle
Saving bits are acknowledged according to the complete acknowledgment principle.
The figure below shows an example of the sequence of the complete acknowledgment
principle in the event of an overflow:
The EVENT_OFLW feedback bit is set as a saving event upon overflow.
You set the RES_EVENT_OFLW control bit to trigger EVENT_OFLW reset.
The RES_EVENT_OFLW_ACK feedback bit is set when reset of EVENT_OFLW is detected.
You then rest the control bit RES_EVENT_OFLW .
The RES_EVENT_OFLW_ACK feedback bit is reset.
Figure 4-5 Acknowledgment principle
Note
If you have initiated the reset of an event bit, you must wait for the respective feedback bit.
Then you can initiate another reset.
software gate or hardware gate (0-1 transition) resets all event bits.