3-6
123
4
5
ABCDEFG
X041E
Siemens-Elema AB SPB7-230.051.07 Page 6 of 18 M1000/3000 Nova
Solna Sweden Rev. 02 03.00 SPS-UD Wiring Diagrams
D801 TESTPOINTS AND LED’s
X812
X813
X816
PROM
CPU
J1
V1
V2
V3
V4
AR
KVA
COLL_ST
GRID_SP
COMP_SP
SPEED
FILT_P
GRID_0
TXD
RXD
0VA1
7V
5V_REF
5V_DSP
X814
X811
F1
0VD1
5V
MPS
X815
F2
V7
V6
V5
S1
RESET SWITCH
CPU BOARD INTERNAL, GENERATOR INTERFACE
~
=
6
5
4
1
3
7
8
2
X811
1
2
X1
12
5
6
3
1
4
11
2
GENERATOR STAND
D700
BACKPLANE
D801
*
KVA
VH
AR
0V_MPS
MPS
GND
COMMUNICATION
T801
BUBN
11V_ MPS
X886A
56
F2
1AT
GENERATOR INTERFACE
FLOATING, GROUNDED BY GENERATOR
V26
0V_MPS
0V_MPS
+5V_MPS
5V_MPS
TXD
RXD
+5V_MPS
0V_MPS
MPS
0V_MPS
0VD1
0VD
80C535
CPU
0VA
*
AR
*
KVA
J1
X112MHz
STATUSLED’s
V1
V2
V3
V4
DATA AND ADDRESS
PROM RAM EEPROM
128k x 8 32k x 8 8k x 8
*
RESET
RESET
0VD
S1
*
RESET SW
*
RESET_HW
+5V
*
RESET
COMP
<4.6V
STATUS LED’s DURING STARTUP:
PROM/RAM TEST V1, V4 LIT.
V2, V3 LIT IF PROM CHECKSUM ERROR.
V3, V4 LIT IF RAM ERROR.
ALL TESTS PASSED, V1-V4 ARE DARK.
X815
0V_MPS
5V_MPS
V26
FOCUS_P
ROT_POS
COLL_P2
COLL_P1
0VD2
X886
56
F802
1AT
I9