Chapter 6
53
possible from the Spectrum is 19200, which equates to a theoretical maximum data
rate of 1745 bytes per second. However, in practice a lower rate will always be
achieved since it takes time to process the bytes that will be sent and those that are
received.
RS232 operation
The RS232 standard defines the voltage levels used to represent data bit values as
-3V to -15V for a logic ‘1’ and +3V to +15V for a logic ‘0’. Normally the data lines will be
idle, which is represented by a logic ’1’ level (referred to as the idle, off or mark state). A
start bit is represented as a logic ’0’ (referred to as the on or space state) and is
therefore distinguishable from the line being in the idle state. Next follow the 8 data
bits of the byte to send, and finally two stop bits which are represented by logic ’1’. The
stop bits in effect put the line back into the idle state.
The procedure used for sending data from the SPECTRA RS232 port is as follows:
The CTS output line should be in the off state (logic ‘1’) and the RX data output line
in the idle state (logic ‘1’). The DTR input line will typically be in the off state
(logic ‘1’).
Set the Comms_Out bit to select RS232 output mode.
Send each byte as follows:
Repeatedly read the DTR input line until the end device signals that it is ready
to receive by setting the line to the on state (logic ‘0’).
Transmit a start bit on the RX data line, which is represented by the on state
(logic ‘0’).
Transmit the data byte on the RX data line, least significant bit first, using a fixed
delay time between bits. The off state is used to represent a binary ‘1’ and the
on state a binary ‘0’.
Transmit two stop bits on the RX data line, which are represented by the off
state (logic ‘1’).
The end device sets the DTR line to the off state (logic ‘1’) while it processes the
received byte.
The RX data and DTR lines are left in the off state (logic ‘1’).
The procedure used for receiving data into the SPECTRA RS232 port is as follows:
The CTS output line should be in the off state (logic ‘1’) and the TX data input line
should be in the idle state (logic ‘1’).
For each byte to receive:
Set the CTS output line to the on state (logic ‘0’) to signal that the end device
may transmit.
Over a fixed length of time repeatedly look for the start bit on the TX data input
line, which occurs when it transitions from the off state (logic ‘1’) to the on state
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